Verilog HDL: Instantiating MAX+PLUS II Primitives
This example describes how to instantiate MAX+PLUS II primitives in Verilog HDL. It instantiates a simple D-type flip-flop, an LCELL primitive, and an open-drain pin.
For more information on using this example in your project, go to:
vprim.v
module vprim (indata, outdata, clock);
input indata, clock;
output outdata;
reg out_dff, out_lcell;
dff d1(.d(indata), .q(out_dff), .clk(clock));
lcell l1(.in(out_dff), .out(out_lcell));
opndrn o1(.in(out_lcell), .out(outdata));
endmodule
The vprim.v design would look like the following diagram if done in schematic format:
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