Verilog HDL: Tri-State Instantiation
This simple example shows how to instantiate a tri-state buffer in Verilog HDL using the keyword bufif1. The output type is tri. The buffer is instantiated by bufif1 with the variable name b1.
For more information on using this example in your project, go to:
tristate.v
module Tristate (in, oe, out);
input in, oe;
output out;
tri out;
bufif1 b1(out, in, oe);
endmodule
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These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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