Verilog HDL: ZBT SRAM Controller
Zero bus turnaround (ZBT) SRAM with No Bus Latency (NoBL) memory is a synchronous burst SRAM with a simplified interface that fully uses the available bandwidth. ZBT SRAM devices use the full bandwidth because they do not require turnaround cycles-i.e., idle cycles between read and write operations. In contrast, standard synchronous burst SRAMs require turnaround cycles, which significantly reduces the available bandwidth.
You can implement the Altera® ZBT SRAM controller reference design in an APEXTM II device to provide a simplified interface to ZBT SRAM. The reference design includes Verilog HDL source files, synthesis and place and route project files, and functional and timing simulation environments.
Download the ZBT SRAM controller reference design:
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
ZBT SRAM Controller System Level Block Diagram
For more information on using this example in your project, go to:
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