The following examples provide instructions for implementing functions using Verilog HDL. For more information on Verilog support, refer to Quartus® II software Help.
For more examples of Verilog designs for Altera® devices, refer to the Recommended HDL Coding Styles (PDF) chapter of the Quartus II Handbook. You can also access Verilog HDL examples from the language templates in Quartus II software. For additional hand-crafted techniques you can use to optimize design blocks for the adaptive logic modules (ALMs) in many Altera devices, refer to the Advanced Synthesis Cookbook: A Design Guide for Stratix II, Stratix III, and Stratix IV Devices (PDF).
Verilog Embedded Processor Functions
- Standard Nios® II Hardware Design Example
- Full-Featured Nios II Hardware Design Example
- Small Nios II Hardware Design Example
- Fast Nios II Hardware Design Example
- Low-Cost Nios II Hardware Design Example
Verilog Communications Functions
Verilog Arithmetic Functions
Verilog External Memory Interfaces Functions
- Four DDR3 ALTMEMPHY-Based Controllers for Stratix IV FPGAs
- Interfacing with a 64-bit DDR3 SDRAM UDIMM interface at 400 MHz in a Stratix IV FPGA
- 36-Bit Wide ALTMEMPHY-Based DDR2 SDRAM Interface for Cyclone® III FPGAs
- 8-Bit Wide DDR2 ALTMEMPHY-Based SOPC Builder Integrated in Cyclone III FPGAs
- Three DDR2 ALTMEMPHY-Based Controllers for Stratix II FPGAs
- 72-Bit Wide DDR2 ALTMEMPHY-Based Interface for Stratix II FPGAs
- 72-Bit Wide DDR2 ALTMEMPHY-Based Interface for Stratix II FPGAs
- 18-Bit Wide QDRII+ ALTMEMPHY-Based Interface for Stratix III FPGAs
- 64-Bit Wide DDR2 ALTMEMPHY-Based Interface for Stratix III FPGAs
- 72-Bit Wide DDR2 SDRAM ALTMEMPHY-Based Interface for Stratix III FPGAs
- Interfacing 400-MHz RLDRAM II in a Stratix IV FPGA
Verilog Memory Functions
- Dual Clock Synchronous RAM
- Single Clock Synchronous RAM
- Parameterized RAM with Separate Input and Output Ports
- Quad Data Rate (QDR) SRAM Controller
Verilog Bus and I/O Functions
Verilog Logic Functions
- 1 x 64 Shift Register
- 8 x 64 Shift Register with Taps
- Counter with Asynchronous Reset
- Instantiating a DFFE
- Synchronous State Machine
Verilog Digital Signal Processing (DSP) Functions
- Verilog HDL Template for Inferring DSP Blocks in Stratix III and Stratix IV FPGAs
- Upgrading an AtlanticTM Interface Design to an Avalon® Streaming Interface Design
- Achieving Unity Gain in Block Floating Point IFFT+FFT Pair
- Coefficient Reload Finite Impulse Response (FIR) Filter
- Fast Fourier Transform (FFT) with 32K-Point Transform Length
- Signed Multiplier with Registered I/O
- Signed Multiply-Adder
- Unsigned Multiplier
- Unsigned Multiply-Accumulator
- 12 x 9 Firm Multiplier
- 12 x 12 Firm Multiplier
- Fully Variable Coefficient Soft Multiplier
- Hybrid Fixed Coefficient Soft Multiplier
- Hybrid Variable Coefficient Soft Multiplier
- Parallel Fixed Coefficient Soft Multiplier
- Parallel Variable Coefficient Soft Multiplier
- Semi-Parallel Fixed Coefficient Soft Multiplier
- Semi-Parallel Variable Coefficient Soft Multiplier
- Sum of Multiplication Fixed Coefficient Soft Multiplier
- Sum of Multiplication Variable Coefficient Soft Multiplier
- Discrete Cosine Transform (DCT)
- Basic FIR Filter
- Time Domain Multiplexed FIR Filter
- Polyphase Decimation FIR Filter
- Polyphase Interpolation FIR Filter
- Two-Dimensional FIR Filter
- Basic Infinite Impulse Response (IIR) Filter
- Butterworth IIR Filter
- Magnitude Function
Other Verilog Functions
How to Use Verilog HDL Examples
Altera provides Verilog HDL design examples as downloadable executable files or displayed as text in your web browser. Select the executable file link to download the file to your hard disk. To use Verilog HDL examples displayed as text in your Quartus II software (or legacy MAX+PLUS® II software), copy and paste the text from your web browser into the Text Editor. Make sure that the file name of the Verilog HDL design file (.v) corresponds to the entity name in the example. For example, if the entity name is my myram, save the file as myram.v.
Design Examples Disclaimer
These design examples may only be used within Altera devices and remain the property of Altera Corporation. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
