VHDL: Cycle-Shared Dual-Port RAM (csdpram)
This example shows the instantiation of the csdpram function in VHDL. Both inputs are 4 bits wide and are 16 words deep. You can customize these parameters by changing the LPM_WIDTH and LPM_WIDTHAD values. If used in a FLEX® 10K device, this function will fit best into the embedded array blocks of the architecture.
For more information on using this example in your project, go to:
cycle.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY altera;
USE altera.maxplus2.ALL;
ENTITY cycle IS
PORT (dataa : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addressa : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addressb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
wea,web : IN STD_LOGIC;
clock : IN STD_LOGIC;
clockx2 : IN STD_LOGIC;
qa : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
qb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END cycle;
ARCHITECTURE lpm OF cycle IS
BEGIN
U1: csdpram
GENERIC MAP (LPM_WIDTH => 4, LPM_WIDTHAD => 4, LPM_NUMWORDS => 16)
PORT MAP (dataa => dataa, datab => datab,
addressa => addressa,
addressb => addressb, wea => wea,
web => web, clock => clock,
clockx2 => clockx2, qa => qa,
qb => qb);
END;
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These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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