VHDL: Converting a Hexadecimal Value to a Standard Logic Vector
This example shows how to convert a hexadecimal value to a std_logic_vector. It is shown in both VHDL '87 (IEEE Std 1076-1987) and VHDL '93 (IEEE Std 1076-1993). For more information on using this example in your project, go to:
hex.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY hex IS
PORT(
D : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END hex;
ARCHITECTURE a OF hex IS
BEGIN
-- The following line will convert the hex value
-- to a STD_LOGIC_VECTOR in VHDL '87.
D(7 DOWNTO 0) <= to_stdlogicvector(x"FC");
-- The following line will work in VHDL '93 (the standard allows
-- this conversion implicitly).
-- D <= x"FC";
END a;
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These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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