VHDL: Counter with Synchronous Load
This example describes a 5-bit counter design with a synchronous load input in VHDL. Synthesis tools look for counter descriptions in HDL code and infer lpm_counter megafunction.
Figure 1. Counter with Synchronous Load Top-Level Diagram
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The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Table 1 lists the ports and gives a description for each.
| Table 1. Counter with Synchronous Load Port Listing |
| Port Name |
Type |
Description |
data |
Input |
5-bit Input data into the counter |
clk |
Input |
Clock |
sload |
Input |
Synchronous load input |
result |
Output |
5-bit counter output |
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