This example describes an 8-bit counter with asynchronous reset input design in VHDL.
Figure 1. Counter with Asynchronous Reset Top-Level Diagram
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The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Table 1 lists the ports in the counter with asynchronous reset design.
| Table 1. Counter with Asynchronous Reset Port Listing | ||
| Port Name | Type | Description |
clk |
Input | Clock input |
| reset | Input | Asynchronous reset |
enable |
Input | Count enable |
q[7:0] |
Output | 8-bit counter output |
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