VHDL: Preventing Unintentional Latch Creation
This example design in VHDL shows how coding style can prevent unintentional latch generation. When CASE or IF statements do not cover all possible input conditions unwanted latches may be generated to hold the output. Including the final ELSE clause or WHEN OTHERS clause in an IF or CASE statement can prevent this unwanted latch from being generated.
Figure 1. Unintentional Latch Creation Top-Level Diagram
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The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Table 1 lists the ports and gives a description for each.
| Table 1. Unintentional Latch Creation Port Listing |
| Port Name |
Type |
Description |
a, b, c |
Input |
Binary inputs |
sel[4:0] |
Input |
5-bit select input |
oput |
Output |
Binary output |
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