This example describes a single clock synchronous parameterized RAM with asynchronous read address in VHDL. Synthesis tools detect RAM designs in HDL code and infer altsyncram or altdpram megafunctions depending on target device architecture.
Download the files used in this example:
- Download single-clk-syncram-asyncrd.zip
- Download Single Clock Synchronous RAM with Asynchronous Read Address README File
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Table 1 lists the ports and gives a description for each.
| Table 1. Single Clock Synchronous RAM with Asynhcronous Read Address Port Listing | ||
| Port Name | Type | Description |
data |
Input | Parameterized data input to RAM |
clock |
Input | Clock |
read_address |
Input | Parameterized asynchronous read address |
write_address |
Input | Parameterized write address |
we |
Input | Write enable input |
q |
Output | Parameterized data output of RAM |
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