This example describes a single port 256-bit x 8-bit ROM design with one address for read operation in VHDL. Synthesis tools detect ROM designs in HDL code and infer altsyncram or lpm_rom megafunctions depending on the target device architecture.
Figure 1. Single Port ROM Top-Level Diagram
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Table 1 lists the ports and gives a description for each.
Table 1. Single Port ROM Port Listing |
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Port Name |
Type |
Description |
addr[7:0] |
Input |
8-bit read address input to ROM |
clk |
Input |
Clock |
q[7:0] |
Output |
8-bit data output of ROM |
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