VHDL: Unsigned Multiply-Adder
This example describes an 8-bit unsigned multiply-adder design with registered I/O ports in VHDL. Synthesis tools detect multiply-adder designs in HDL code and infer altmult_add megafunction.
Figure 1. Unsigned Multiply-Adder Top-Level Diagram
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The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Table 1 lists the ports and gives a description for each.
| Table 1. Unsigned Multiply-Adder Port Listing |
| Port Name |
Type |
Description |
a, b, c, d |
Input |
8-bit inputs to multiply-adder unit |
clk |
Input |
Clock |
aclr |
Input |
Asynchronous clear |
result |
Output |
16-bit output of multiply-adder unit |
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