VHDL: ZBT SRAM Controller
Zero bus turnaround (ZBT) SRAM with No Bus Latency (NoBL) memory is a synchronous burst SRAM with a simplified interface that fully uses the available bandwidth. ZBT SRAM devices use the full bandwidth because they do not require any turnaround or idle cycles between read and write operations. In contrast, standard synchronous burst SRAM devices require turnaround cycles, which significantly reduce the available bandwidth.
You can implement the Altera® ZBT SRAM controller reference design in a Stratix® (see figure 1 for the block diagram) or APEX™ II device (see figure 2 for the block diagram) to provide a simplified interface to ZBT SRAM. The reference design includes VHDL source files, synthesis and place and route project files, and functional and timing simulation environments.
The following ZBT SRAM controller reference designs are available for download:
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Figure 1. ZBT SRAM Controller System Level Block Diagram for Stratix & Stratix GX
Figure 2. ZBT SRAM Controller System Level Block Diagram for APEX II
For more information on using this example in your project, go to:
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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