Altera为三速以太网MegaCore®功能提供大量的文档和强大的支持，帮助您轻松快捷的开发调试以太网应用，例如10/100 Mbps (快速以太网)和1000 Mbps (千兆以太网)线路卡、NIC卡以及交换机等。
资料
应用笔记
- AN 440：加速Nios II网络应用 (PDF)
- AN 477：采用HardCopy设计RGMII接口 (PDF)
- AN 483：三速以太网数据通路参考设计 (PDF)
- AN 518：使用Stratix III器件的软核CDR模式实现SGMII接口 (PDF)
- AN 585：使用三速以太网测试台进行仿真调试 (PDF)
参考设计
设计实例
Altera知识数据库
知识数据库提供支持解决方案，回答常见问题，提供关于三速以太网MegaCore功能已知问题的信息。
以下是经常被参考的解决方案：
中文版：
- 为什么当我的设计包含Lan91c111接口和Altera的三速以太网IP核时，Nios II在初始化设备的时候会失败？
- 三速以太网的Avalon-ST收发接口的数据格式是什么样的？
- 在10/100Mbps模式下，当MAC的本地回环启用后，为什么三速以太网IP MegaCore会指示接收数据包错误？
- 在半双工模式下，为什么三速以太网IP MegaCore在冲突出现后，MAC模块的发送通路没有发送重传帧？
- 在半双工模式下，为什么三速以太网IP MegaCore在冲突出现后，MAC模块的发送通路没有发送重传帧？
- 在半双工模式下，为什么三速以太网IP MegaCore在冲突出现后，即使没有数据送给MAC模块，MAC模块仍继续通过MII接口发送出数据？
- 为什么三速以太网IP MegaCore的统计计数器aFrameReceivedOK和etherStatsUndersizePkts在MAC模块接收到magic数据包并被唤醒后加了1？
- 为什么三速以太网IP MegaCore的MAC功能工作于睡眠模式时，而统计计数器却工作在正常模式？
- 为什么三速以太网IP MegaCore的统计计数器 ifOutErrors，ifOutUcastPkts，ifOutMulticastPkts和ifOutBroadcastPkts对由延迟冲突（late collision）和过度冲突（excesive collision）导致的丢包没有统计？
- 为什么三速以太网IP MegaCore的统计计数器aFramesReceivedOK, aOtetsReceivedOK, etherStatsOctets, etherStatsPkts和etherStatsPkts64Octets在收到pause帧时会额外多加1？
- 为何有时DFE不能返回最佳参数？
- 为什么三速以太网MegaCore从10/100Mbps到1000Mbps模式改变后会出现错误的数据包？
- 为什么三速以太网MegaCore从10/100Mbps到1000Mbps模式改变后会出现错误的数据包？
- 三速以太网（TSE）多端口配置（PCS+PM）)配置是否需要PLL的合并？
英文版：
- Why will the physical medium attachment (PMA) of Triple Speed Ethernet intellectual property (IP) MegaCore function automatically undergo the reset sequence whenever rx_freqlocked is lost?
- Why does fitting error occur for Triple Speed Ethernet IP MegaCore® in the Cyclone® IV GX device?
- Why don't reset_rx_clk and reset_tx_clk signals of PCS-only variant and PCS-plus-PMA variant of Triple Speed Ethernet IP MegaCore synchronize to rx_clk and tx_clk?
- Why do Triple Speed Ethernet IP MegaCore instance’s transmit and receive PLL for LVDS I/O fail to share the same PLL?
- Why do multiple Triple Speed Ethernet IP MegaCore instances with LVDS I/O fail to share the same PLL?
- Why do multiple Triple Speed Ethernet IP MegaCore instances with LVDS I/O fail to share the same PLL?
- Why do multiple Triple Speed Ethernet IP MegaCore instances with transceivers fail to fit into the same transceiver Quadrant?
- Why don't statistics counters aOctetsReceivedOK and etherStatsUndersizePkts of Triple Speed Ethernet IP MegaCore count on the length of pause frame when pause frame forward is disabled while received?
- Why are statistics counters ifOutUcastPkts and ifOutBroadcastPkts of Triple Speed Ethernet IP MegaCore not increased when erroneous unicast and broadcast frame are transmitted?
- Why will the first packet transmitted be lost when Triple Speed Ethernet MegaCore function with 8 bits of internal ST FIFO MAC with PCS operate in 10/100 Mbps mode?
- Why does packet error occur after the mode changes from 10/100 Mbps to 1000 Mbps for Triple Speed Ethernet MegaCore?
- When Triple Speed Ethernet IP MegaCore in 10/100-Mbps mode receives large packet size (e.g. 1518 byte) in SGMII mode, the packet might be corrupted.
- Why is there a reconfig_clk frequency discrepancy between the device handbook and the Triple-Speed Ethernet (TSE) User Guide?
- Which Triple Speed Ethernet MAC registers must be set to run a simulation?
- Why does the Altera Triple Speed Ethernet MegaCore function have an error during synthesis?
- In the Altera® Triple Speed Ethernet MegaCore function, how is the PCS register address calculated?
- How are the Triple Speed Ethernet register addresses in SOPC Builder calculated for the Altera Triple Speed Ethernet MegaCore function?
从这里找到三速以太网MegaCore功能的其他解决方案。
在线培训课程
开发套件
为三速以太网MegaCore功能提供以下开发套件：
