文档资料 许可 在线购买 下载 全部页面 技术资料 产品型号

主页   |   产品   |   支持   |   最终市场   |   技术中心   |   教育与活动   |   公司介绍   |   在线购买

mySupport   |   器件   |   软件   |   IP   |   设计范例   |   参考设计

嵌入式处理器    Nios II 嵌入式设计套件       Nios II 开发套件     DSP       Overview       DSP Builder       IP Cores       开发套件

主页 > 支持 > IP > Interfaces and Peripherals IP Cores 打印此页 发送此页 Interfaces and Peripherals IP Cores The Interfaces and Peripherals intellectual property (IP) functions from Altera provide system-on-a-programmable-chip (SOPC) integration, offer flexible peripherals, and support a wide variety of standard bus interfaces. Altera's rapidly growing portfolio of standard bus interfaces allows users to add chip-to-chip, board-to-board, or box-to-box connectivity to SOPC designs. The  portfolio also includes megafunctions to seamlessly add external memory, PCI, HyperTransport and other next-generation interfaces. Altera provides support for the following Interfaces and Peripherals MegaCore® functions. PCI Compiler PCI Compiler: 32-Bit Master/Target MegaCore Function PCI Compiler: 32-Bit Target MegaCore Function PCI Compiler: 64-Bit Master/Target MegaCore Function PCI Compiler: 64-Bit Target MegaCore Function PCI Compiler User Guide (PDF) PCI Compiler Errata Sheet (PDF) AN 330: Connecting Altera® 3.3-V PCI Devices to a 5-V PCI Bus (PDF) AN 223: PCI-to-DDR SDRAM Reference Design (PDF) PCI Constraint Files Solutions/Find Answers - PCI HyperTransport MegaCore Function HyperTransport (HT) MegaCore Function HyperTransport MegaCore Function User Guide (PDF) HyperTransport MegaCore Function Errata Sheet (PDF) RapidIO MegaCore Function RapidIOTM MegaCore Function RapidIO MegaCore Function User Guide (PDF) RapidIO MegaCore Function Errata Sheet (PDF) SerialLite/SerialLite II MegaCore Function SerialLite MegaCore Function User Guide (PDF) SerialLite Megacore Function Errata Sheet (PDF) SerialLite II MegaCore Function SerialLite II MegaCore Function User Guide (PDF) SerialLite II Megacore Function Errata Sheet (PDF) Memory Controllers DDR SDRAM Controller MegaCore Function DDR2 SDRAM Controller MegaCore Function QDRII SRAM Controller MegaCore Function DDR & DDR2 SDRAM Controller Compiler User Guide (PDF) QDRII SRAM Controller MegaCore Function User Guide (PDF) DDR & DDR2 SDRAM Controller Compiler Errata Sheet (PDF) DDR & DDR2 SDRAM Controller Compiler FAQ White Paper (PDF) The Efficiency of the DDR & DDR2 SDRAM Controller Compiler White Paper (PDF) AN 361: Interfacing DDR & DDR2 SDRAM With Cyclone™ II Devices (PDF) AN 348: Interfacing DDR SDRAM with Cyclone Devices (PDF) 给本页评分   相关链接 Intellectual Property (IP) MegaStore Licensing Solutions / Find Answers     注册索取最新邮件通知

请填写反馈意见   注册索取最新邮件通知

主页 | 产品 | 支持 | 最终市场 | 技术中心 | 教育与活动 | 公司介绍 | 在线购买  mySupport | 器件 | 软件 | IP | 设计范例 | 参考设计  联系我们 | 站点帮助 | 网站导航 | 个人信息 | 法律申明  Copyright © 1995-2008 Altera International Limited, 香港九龙观塘观塘道388号创纪之城1期1座9楼11-18室 Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus和MegaCore是Altera公司的商标。