- Nios II Processor Core
- Peripherals
- SOPC Builder & Quartus II Software
- Host Platform
- Device
- Development Boards
- Download Cables & Debug Hardware
- Hardware Simulation
- Configuration & Booting
Nios II Processor Core
This section lists any issues related to the Nios® II processor cores.
There are no known issues at this time.
Peripherals
This section lists any issues related to the Nios II peripherals included in the Nios II Development Kits.
JTAG UART is unstable after device-wide reset.
SPI Core clock synchronization issueIf the DEV_CLRn pin on the FPGA input has been assigned (in the Quartus® II software) to generate a device-wide reset, and the FPGA is reset while the JTAG UART is active, then the JTAG UART might become unstable.
Workaround: Do not use the DEV_CLRn function on the FPGA. Turn off the Enable device wide reset (DEV_CLRn) setting in the Quartus II software.
SPI master selectIssues with the synchronization logic between clk and sclk may cause invalid data on the SPI slave core.
Workaround: Please contact Altera support for potential workarounds.
SPI master Specify Delay option provides incorrect resultsThe SPI master core does not select the correct slave device until a data transfer has started. The previous slave will be selected again first, and then the appropriate slave is selected.
Workaround: Please contact Altera support for potential workarounds.
If the Specify Delay option is used, the delay set may not take effect. Instead, no delay will occur in most systems.
Workaround: Please contact Altera support for potential workarounds.
SOPC Builder & Quartus II Software
Quartus II compilation fails due to limited PLL resourcesRunning the Nios II IDE from SOPC Builder doesn't workQuartus II compilation may fail for Nios II systems using the highest debug level if inadequate PLL resources are available in the target FPGA. The external trace debug feature of the Nios II JTAG debug module (which is enabled in the highest debug level) uses a hidden instantiation of a PLL.
Workaround: Possible workarounds include:
- Choosing a debug level without external trace
- Deleting or combining PLLs to reduce PLL resource usage
- Feeding the SOPC Builder clock directly from an external pin instead of from an internal PLL
- Using the "full_featured" Nios II example design as a platform for system development, which has special allowances to use 1 PLL for both system clock and external trace clock.
In SOPC Builder on the System Generation tab, the Run Nios II IDE button (or Tools > Nios II IDE) might not work in certain known cases.
Workaround: Attempting to launch the Nios II Integrated Development Environment (IDE) from SOPC Builder will have no effect if there is already an instance of the Nios II IDE running. If the Nios II IDE previously terminated abnormally, it might have left a .lock file in the directory <Nios II kit path>/bin/eclipse/workspace/.metadata, and on Windows PCs it might have left a lingering javaw.exe process. Close any running instances of the Nios II IDE, manually delete the .lock file and terminate any javaw.exe processes, then try again.
Host Platform
This section lists any issues related specifically to the host platform.
Linux: The Quartus II stand-alone programmer is not supported on LinuxLinux: The Flash Programmer GUI fails to program flash on LinuxOn Linux, the Nios II IDE cannot launch the Quartus II stand-alone programmer. As a result, in the Nios II IDE the Tools > Quartus II Programmer command has no effect, and the IDE does not automatically launch the programmer when you attempt to download software to a board that does not match the expected hardware image.
Workaround: Launch the Quartus II software to access the Quartus II Programmer.
Frisk antivirus software causes SOPC Builder and Nios II SDK to be unresponsiveOn Linux systems, the Nios II IDE Flash Programmer utility might fail to complete the flash programming process. In this case, the IDE Console view will display messages indicating that the Quartus II programming file conversion utility was called, but never proceeds beyond that point.
Workaround: You can successfully program flash by executing an auto-generated script from a command line. Perform the following steps:
- If the Flash Programmer is active but not advancing, click Cancel.
- Ensure that the Quartus II convert-programming-files process has been terminated. Use the Linux ps utility to check for quartus_cpf processes. Terminate any existing quartus_cpf processes.
- Open a shell window and start the Nios II SDK shell by navigating to the <Nios II kit path> directory and executing the sdk_shell script.
- In the SDK shell, cd to the Debug or Release subdirectory of the Nios II IDE project you want to program to flash. In this directory you will find a .sh script that was created by the Flash Programmer. The script file will be named similarly to the flash programming configuration you created in the Nios II IDE Flash Programmer GUI (e.g., hello_world_0_programmer.sh).
- Execute the .sh script by typing the following:
sh <Path to project>/<Debug|Release>/<name of Flash Programmer configuration>.shThe full flash programming process should progress normally. You can change the script programs to flash by updating the Flash Programmer configuration in the GUI and clicking Apply. The IDE will use your new settings and regenerate the .sh script.
The SOPC Builder and Nios II SDK Shell may become unresponsive if run while the Frisk antivirus software is running.
Workaround: Turn off the Dynamic Virus Checking feature of the Frisk software before running SOPC Builder or the Nios II SDK Shell.
Device
This section lists any device-related issues.
Stratix II EP2S60 ES devices cannot use MRAM byte enablesEarly shipments of the Nios development board, Stratix® II Edition include an EP2S60 engineering sample (ES) device. Stratix II EP2S60 ES devices have a silicon problem that prevents the use of byte enables on MRAM blocks. Refer to the Stratix II FPGA Family Errata Sheet for details. Because of this issue, the Quartus II software does not allow you to directly instantiate an MRAM block with byte enables in designs targeting EP2S60ES devices.
Workaround: Stratix II production devices (non-ES) will support MRAM byte enables.
Development Boards
This section lists any issues related to Nios II development boards.
CompactFlash card and LCD screen don't work concurrentlyNetworking ExamplesIf there is a CompactFlash card inserted in the development board, the LCD and other devices connected to the PROTO1 header might not work.
Workaround: Remove the CompactFlash card to ensure proper operation of the PROTO1 header, or vice versa.
When running a networking example design, you are asked for a 9-digit number after the letters 'ASJ' and your Nios II development board does not have a sticker with a 9-digit number after the letters 'ASJ'.
Workaround: Enter a unique 9-digit number when prompted. Ensure that this number is unique to each Nios board connected to your network to avoid network address conflicts.
Download Cables & Debug Hardware
This section lists any issues related to download cables and other debug hardware.
Communication errors during run/debug sessions using older download cables
Debugging with the following Altera download cables might fail, due to electrical noise-related JTAG communication failures: USB-Blaster™ Rev A, ByteBlaster™, ByteBlasterMV™, ByteBlaster II, and MasterBlaster™ cables.
Currently, the only fully supported cable for downloading, debugging, or communicating with Nios II systems is the USB-Blaster Rev B or later. Revision B cables are clearly labeled as Revision B. (Revision A cables have no revision label.)
Workaround: Use a USB-Blaster Rev B cable. Older cables can be used, but they might encounter JTAG communication failures. Please note that you may still get benign warning messages if using a USB-Blaster Rev B cable shipped before January 30, 2005 due to a known issue with the identification firmware. These warnings can be ignored. USB-Blaster cables with the gold-colored flexible PCB cable are the solution to the JTAG communication failures.
Hardware Simulation
This section lists issues related to simulating Nios II processor systems on an RTL simulator, such as the ModelSim® simulator.
Uninitialized BSS variables in simulation"No printer selected" error when attempting ModelSim SimulationIf your program reads the value of an uninitialized BSS variable during HDL simulation when the HAL system library has been compiled with the 'Modelsim only, no hardware support' property enabled in Nios II IDE, a warning will be produced about unfiltered data being ‘x’. This occurs because when this property is enabled, the code that clears the BSS memory region is omitted to speed up HDL simulation so this memory region is uninitialized.
The BSS region contains global and static local variables that are not initialized by the application so they default to a value of zero. When the Nios II CPU reads uninitialized variables, it displays a warning and converts any of the bits of the uninitialized data to zero which correctly mimics the effect of the missing BSS clearing code. The HAL code that executes before and after main() may use BSS variables so these warnings may be generated even if your application doesn’t use the BSS.
Workaround: None available at this time.
ModelSim fails to load large memory modelsIf you did not enable the simulation option in SOPC Builder when generating the system, and attempt Run As > Nios II Modelsim in the Nios II IDE, you will get an error stating that you there are no simulation files. This might also generate a benign error stating "no printer selected" if your host system has no printers enabled.
Workaround: To successfully simulate your design, enable the simulation option in SOPC Builder, regenerate, and perform the Run As...Nios II Modelsim in the IDE again.
ModelSim might fail to load simulation models for memory arrays larger than 128M bytes, halfwords or words in size. If the sum of the following parameters is greater than 27, ModelSim will fail to load:
- address_bits (i.e. 14)
- column bits (i.e. 11)
- log2(number of banks) (number of banks is usually 4, so this term is usually 2)
- log2(chipselects) (number of chipselects is usually 1, so this term is usually 0)
Workaround: Simulate using a smaller SDRAM than the SDRAM implemented in hardware. This is possible if the entire memory space doesn’t need to be simulated.
Configuration & Booting
Errors when booting from EPCS Device
The EPCS flash controller contains an on-chip memory populated with boot-loader code. Users who direct Nios II to boot (reset) from EPCS flash will execute this software on power-up, configuration, or system reset. The boot loader in Nios II 1.1 points to an incorrect offset within the EPCS controller, causing the system to fail to load Nios II software. The following patch corrects this behavior. Follow the instruction in the readme.txt included in the patch.
EPM7128 Configuration Controller Designs not included in Nios II version 1.1
The configuration controller designs previously installed with the Nios II Development Kits were mistakenly omitted from the version 1.1 installation. The designs for each Nios II Development Kit can be downloaded here:
