解决方案ID: rd05122009_524
最后修改: 2011 年12 月29 日
产品类别: IP
产品领域: 其他(IP)
产品子领域: 其他 (IP)
IP产品: PCI Express 1/2/4/8 Lanes (x8)

标题

PCI Express 编译器用户指南：已知问题

说明

问题: 361429 第五章 "PCI Express® Reconfiguration Block Signals—Hard IP Implementation"

在 PCIe IP中avs_pcie_reconfig_clk 信号最高频率为50MHz，使用更高的频率会导致在dprioout 总线上出现setup时序违规。

问题: 336210 第五章 "Signals"

请忽略 PCI Express User Guide第5-1页中的下列句子：

"The hard IP implementation is not available for designs using the Avalon-MM interface."

问题: 309948 第四章  "Functional Description": Clocking部分

在文档的clocking部分中讨论了下面的几个配置：

• MegaWizard™ Plug-In Manager Design Flow Clocking—Hard IP Implementation
• MegaWizard Plug-In Manager Design Flow Clocking—Soft IP Implementation
• SOPC® Builder Design Flow Clocking—Soft IP Implementation

其中并没有讨论"SOPC Builder Design Flow Clocking—Hard IP Implementation"，但是"SOPC Builder Design Flow Clocking—Soft IP Implementation "中的信息适用于Hard IP实现。

问题: 309946 第四章  "Functional Description": Clocking部分

"Figure 4–23. SOPC Builder - Separate Clock Domains"信息缺失。

该图应该显示两个时钟Ref_clk和clk输入到PCI Express Megacore ® Avalon ® MM模块。在"Table 5–39. Avalon-MM Clock Signals "中讨论了这两个时钟，但是并没有显示在"Fiqure 4-23"。

问题: 307753 第五章  "Signals": Avalon®-ST  Interface部分

下面对于"Table 5–2. 64- or 128-Bit Avalon-ST Rx Datapath States "这种对于rx_st_bardec0信号的描述：

"The decoded BAR bits for the TLP. They correspond to the transaction layer's rx_desc[135:128]. They are valid on the 2nd cycle of rx_st_data0. "

对于64-bit数据通路文档是正确的，descriptor 将消耗两个时钟周期。

上面的声明并不适用于了128-bit接口，对于128bit数据通路，descriptor将只消耗一个时钟周期，所以bardec在第二个周期是无效的。

问题: 314540 第五章 "Signals": Avalon-ST  Interface部分

Table 5-16 显示一个12 bit 信号(cfg_np_bas[11:0]) 被压缩为8 bit，该消息是错误的。This cfg_np_bas是一个12-bit signal。 Table 5-16 中地址7(DW 7) 正确的映射如下：

Bits[31:24] = 全 0

Bits[23:12] = tl_cfg_ctl[23:12]

Bits[11:0] = cfg_np_lim[11:0]

问题: 321267 第五章 "Signals": Reset Signals部分

"Table 5–8. Reset Signals (Part 2 of 2)"讨论了reset_status信号, 但是没有提供信号如何得来的细节。

下列文字将会加入到Quartus® II 用户手册的9.1版本中：

"The reset_status signal is a function of srst and crst. When one of these two signals asserts, reset_status is asserted. When the npor signal asserts, reset_status is reset to zero."

问题: 321274 第四章 "Functional Description " : Architecture部分

在Table 4-2中给出了详细的事务顺序规则。

下列文字将会加入到Quartus II 用户手册的9.1版本该部分中，"MSI request are conveyed in exactly the same manner as PCI Express Memory Write request and are indistinguishable from them in terms of flow control, ordering, and data integrity."

问题: 321277 第四章 "Functional Description" ECRC Section

关于在使能ECRC forwarding后，用户应用如何显示有ECRC错误的信息并没有包含在用户手册上。因而下面的信息将会加入到Quartus II 用户手册的9.1版本中：" When the application detects an ECRC error, it should send the ERR_NONFATAL message TLP to the PCI Express MegaCore function to report the error.For more information about error handling, refer to the Error Signaling and Logging which is Section 6.2 of the PCI Express Base Specification, Rev. 2.0."

问题: 321281 第五章 "Signals": Reset Signals部分

在用户手册中没有关于reset_status信号时钟同步驱动的信息。下面的信息将会加入到Quartus II 用户手册的9.1版本中：" the reset_status signal is synchronous with the pld_clk. So the reset_status signal will be deasserted only when pld_clk is stable."

问题: 321282 第五章: "Signals" Completion Side Band Signals Section

Quartus II 用户手册的9.1版本中将会更新cpl_err[6..2]描述信息：

cpl_err[2]:Completer abort error. The application asserts this signal to respond to a posted or non-posted request with a completer abort (CA) completion. In the case of a non-posted request, the application generates and sends a completion packet with completer abort (CA) status to the requestor and then asserts this error signal to the MegaCore function. The MegaCore function automatically sets the error status bits in the configuration space register and sends error messages in accordance with the PCI Express Base Specification.

cpl_err[3]:Unexpected completion error. This signal must be asserted when an application layer master block detects an unexpected completion transaction. Many cases of unexpected completions are detected and reported internally by the transaction layer of the MegaCore function. For a list of these cases, refer to "Errors Detected by the Transaction Layer" on page 4–54.

cpl_err[4]: Unsupported request error for posted TLP. The application asserts this signal to treat a posted request as an unsupported request (UR). The MegaCore function automatically sets the error status bits in the configuration space register and sends error messages in accordance with the PCI Express Base Specification. Many cases of unsupported requests are detected and reported internally by the transaction layer of the MegaCore function. For a list of these cases, refer to "Errors Detected by the Transaction Layer" on page 4–54.

cpl_err[5]: Unsupported request error for non-posted TLP. The application asserts this signal to respond to a non-posted request with an unsupported request (UR) completion. In this case, the application sends a completion packet with the unsupported request status back to the requestor, and asserts this error signal to the MegaCore function. The MegaCore automatically sets the error status bits in the configuration space register and sends error messages in accordance with the PCI Express Base Specification. Many cases of unsupported requests are detected and reported internally by the transaction layer of the MegaCore function. For a list of these cases, refer to "Errors Detected by the Transaction Layer" on page 4–54

cpl_err[6]: Log header. When asserted, logs err_desc_func0 header. Used in both the soft IP and hard IP implementation of the MegaCore function that use the Avalon-ST interface. When asserted, the TLP header is logged in the AER header log register if it is the first error detected. When used, this signal should be asserted at the same time as the corresponding cpl_err error bit (2, 3, 4, or 5). In the soft IP implementation, the application presents the TLP header to the MegaCore function on the err_desc_func0 bus. In the hard IP implementation, the application presents the header to the MegaCore function by writing the following values to 4 LMI registers before asserting cpl_err[6]:

¨lmi_addr: 12'h81C, lmi_din: err_desc_func0[127:96]

¨lmi_addr: 12'h820, lmi_din: err_desc_func0[95:64]

¨lmi_addr: 12'h824, lmi_din: err_desc_func0[63:32]

¨lmi_addr: 12'h828, lmi_din: err_desc_func0[31:0]

Refer to the "LMI Signals—Hard IP Implementation" on page 5–34 for more information about LMI signalling.

For the ×8 soft IP, only bits [3:1] of cpl_err are available. For the ×1, ×4 soft IP implementation and all widths of the hard IP implementation, all bits are available.

问题: 323073 第五章: "Signals " Avalon-ST Interface部分

下列输入在PCI Express编译器用户手册中被描述为 "for simulation only"，但是并没有提及在你的RTL中如何连接他们：

p_clk_in

rxdata0_ext

rxdatak0_ext

rxvalid0_ext

phystatus_ext

rxelecidle0_ext

rxstatus0_ext

下面的文字将会加入到Quartus II 用户手册的9.1版本中： " For variants that use the internal transceiver, these signals are for simulation only. For Quartus II software compilation, these pipe signals can be left floating. "

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