10-Gbps Ethernet Hardware Demonstration Reference Design

from Altera

Overview

Altera's 10-Gbps Ethernet Hardware Demonstration reference design provides a quick way to implement your 10-Gigabit Ethernet (10 GbE)-based design in an Altera^® FPGA, and observe live network traffic flowing through various sections of a system. This design also helps you to verify your 10-GbE-based system operation with an Altera 10-GbE media access controller (MAC) function and a standard off-the-shelf 10-GbE physical medium dependent (PMD) device. The Altera 10-GbE MAC is validated by the University of New Hampshire Interoperability Laboratory (UNH-IOL). You can leverage this reference design to build your own 10-GbE system with low risk and minimal effort.

The reference design is built with Altera's SOPC Builder using an instance of the Altera 10-GbE Reference Design function and four 3.125-Gbit serial transceivers in a Stratix^® IV GX or Arria^® II GX FPGA to implement one 10-GbE XAUI port. This reference design demonstrates the operation of the 10-GbE function up to the maximum wire-speed performance in many loopback hardware configurations, as shown in Figure 1.

Features

• Showcases one instance of the Altera^® 10-GbE reference design function supporting 10-Gbps Ethernet operations in XAUI mode.
• Demonstrates sending, receiving, and automatic checking of Ethernet frames up to the maximum theoretical wire data rate.
• Can flexibly be set to many configuration options, as shown in Figure 1. The configurations shown allow several test and demonstration scenarios.
  • Options A, B, and C: One port external local loopback (transmitter looped back to receiver) respectively at the CX4 connector, X2 optical fiber module, and high-speed mezzanine card (HSMC) connector. These options allow external self testing to verify the functionality of 10-GbE MAC+PCS+PMA while passing the data through the external HSMC connector, HSMC adapter, and CX4 loopback device or fiber optic loopback cable assembly.
  • Options D and E: One port internal local loopback respectively at the PMA serial interface and at the MAC internal XGMII interface. These options allow internal on-chip MAC+PCS+PMA and MAC-only self testing, respectively.
  • Option F: One port internal line MAC loopback (receiver looped back to transmitter at MAC internal system interface) for compliance or interoperability testing by external test equipment or a legacy 10-Gbps Ethernet system.
• Jump-starts your embedded system design/performance evaluation.
  • Minimal hardware requirements: A host computer and an Altera USB-Blaster^TM or ByteBlaster^TM cable assembly, a Stratix IV GX FPGA development kit or an Arria II GX FPGA development kit, an X2 HSMC adapter and an optical X2 pluggable module, or a CX4 HSMC adapter from MorethanIP or an HSMC loopback.
  • Programmable settings include number of frames, frame length, and payload data type.
  • Step-by-step walk-through instructions, complete design files (including Quartus^® II software archive), and Windows XP-based software application for test control and monitoring are provided.

Demonstrated Altera Technology

• Stratix IV GX FPGAs
• Arria II GX FPGAs
• Altera 10-Gbps Ethernet Reference Design function
• Nios^® II embedded processor intellectual property (IP) cores
• Altera CRC Compiler MegaCore^® function
• Nios II Embedded Design Suite (EDS)
• SOPC Builder
• Avalon^® system interconnect

Block Diagrams

Figure 1 shows test and loopback configurations.

Figure 1. 10-Gbps Ethernet Hardware Demonstration Reference Design Illustrating Test and Loopback Configurations (1)

Note:

1. The X2 HSMC is available only for demonstration and cannot be ordered. Contact your local Altera sales representative to obtain this card.

Figure 2 shows a two-port external loopback test for self testing on two development kits.

Figure 2. 10-Gbps Ethernet Hardware Demonstration Reference Design in External Two-Port Local Loopback Test Configuration

Related Links

• Stratix IV GX FPGAs
• Arria II GX FPGAs 
• Altera 10-Gbps Ethernet XAUI solution
• Altera 10-Gbps Ethernet Reference Design function
• Altera Nios II MegaCore Function
• Altera CRC Compiler Megacore function
• Altera Nios II EDS
• Altera SOPC Builder
• Stratix IV GX FPGA Development Kit
• AN 516: 10-Gbps Ethernet Reference Design (PDF)
• AN 588: 10-Gbps Ethernet Hardware Demonstration Reference Designs (PDF)

Reference Designs Disclaimer

These reference design illustrations may be used within Altera Corporation devices only and remain the copyrighted property of Altera. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.