10-Gbps Ethernet Reference Design
from Altera Corporation
Please contact your local Altera sales representative for a copy of this reference design. The use of this design is governed by, and subject to, the terms and conditions of an Altera Reference Design License Agreement.
Overview
Altera’s 10-Gbps Ethernet (10-GbE) reference design provides a flexible, feature-rich IEEE 802.3ae-2002 standard-compliant intellectual property (IP) solution for implementing 10-GbE or N x 10-GbE line cards in an Altera® FPGA. The 10-GbE reference design provides a hardware-tested block for implementing a variety of Ethernet-based communication and broadcast systems such as network routers, LAN, metro, core, and MSPP switches and new broadcast studio and distribution equipment.
The Altera 10-GbE reference design consists of a 10-GbE MAC IP and optionally a 10GBASE-X Physical PCS. This reference design provides an XGMII or XAUI external interface to easily connect the system logic to a variety of standard 10-GbE PHY devices and optical transceiver modules. The 10GBASE-X PCS option and XAUI interface can be implemented in hard silicon in Altera FPGAs with gigabit serial transceivers.
Figure 1. 10-GbE Reference Design in an Altera FPGA
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Features
- Complete solution, including intellectual property (IP) and user configuration MegaWizard® software
- Compliant to IEEE802.3ae-2002 specifications
- Passed the University of New Hampshire Interoperability Lab (UNH) 10 Gigabit Ethernet tests of MAC, PCS and PMA
- Verified with simulation models and tested with third-party test equipment
- 10-GbE MAC standard functions in full-duplex
- Promiscuous and non-promiscuous modes
- Programmable maximum frame length up to 16 Kbytes
- Programmable inter-frame gap
- Deficit idle counter (DIC) support
- Supported in Stratix® IV, Stratix III, Stratix II, Stratix II GX, and ArriaTM GX FPGA families
- Flexible standard interfaces:
- Seamless interface to external Ethernet PHY device via XAUI or XGMII
- Management data I/O (MDIO) master interface for PHY device management
- Internal 64-bit datapath interface to system logic based on the Avalon®-Streaming (Avalon-ST) high-performance interface
- Parameterizable FIFO (64 bytes to 64 Kbytes) and non-FIFO options for low latency
- Internal 32-bit management slave interface based on the Avalon-Memory-Mapped Interface (Avalon-MM)
- Virtual LAN (VLAN) and stacked VLAN tagged frames support according to IEEE 802.IQ
- Option for local or line loop-back at RS sub-layer for easy system test
- Network management feature: Option for statistics counters for SNMP Management Information Base (MIB and MIB-II) and remote network monitoring (RMON)
- Easy-to-use MegaWizard interface for configuring and generating the 10-GbE
- Altera SOPC Builder compliant for quick and easy system design
- IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators
Technical Support
For technical support on this reference design, please visit the Altera mySupport online issue tracking system. You may also search for related topics on this function in the Altera Solutions Database.
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Reference Designs Disclaimer
These reference design illustrations may be used within Altera Corporation devices only and remain the copyrighted property of Altera corporation.
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