AES3/EBU Reference Design
from Altera Corporation
Overview
The Audio Engineering Society together with the European Broadcasting Union have developed the AES3/EBU digital audio transmission standard, a serial point-to-point interface that carries digital audio data over a standard cable. Audio data is typically in pulse code modulation (PCM) format. The AES3/EBU reference design also supports compressed audio and non-audio data transmission. The information sent over the AES3/EBU is non-return to zero (NRZ) coded with the bi-phase mark (BPM) code so clock and data can be recovered on the receive side of the interface.
The AES3/EBU reference design provides both a transmitter and a receiver. The receiver extracts the data and the clock from an incoming AES3/EBU stream, and stores the parallel audio data and control bits into a FIFO buffer.
The received information can be extracted from the FIFO buffer for processing, or sent directly to the transmitter. The AES3/EBU nominal data rate is directly related to the source audio sample rate. The receiver's input data rate is set at compile time to a fixed frequency, supporting PCM sample rates up to 192 kHz.
The transmitter takes parallel data from a FIFO buffer, performs serialization, parity bit generation, bi-phase coding, and appends the appropriate X,Y, Z header. It performs null-packet stuffing when no audio data is present in the transmit FIFO buffer. The transmit clock may be derived from an asynchronous source or it may be locked to an extracted receive clock via an external voltage-controlled crystal oscillator (VCXO).
Altera supplies the AES3/EBU reference design as Verilog HDL source code. The reference design includes transmit and receive blocks, testbenches which allow testing of the Verilog HDL source code, Quartus® II implementation constraints, and demonstrations that run on Altera Stratix® GX and CycloneTM Video Demonstration Boards.
If the electrical interface for Sony/Philips digital interface (S/PDIF) is adhered to, the reference design can also address the S/PDIF. For S/PDIF, some differences exist in the interpretation of the channel status block registers, but the reference design needs no changes for S/PDIF.
Block Diagram
Figure 1 shows the reference design block diagram.
Enlarge View
Features
- AES3/EBU transmit and receive functionality
- Control channel status block capture on the receiver
- Control channel status block insertion for the transmitter
- Hardware cyclic redundancy check (CRC) checking on the receiver
- Hardware CRC generation on the transmitter
- S/PDIF compatibility
Related Links
Reference Designs Disclaimer
These reference design illustrations may be used within Altera Corporation devices only and remain the copyrighted property of Altera. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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