Avalon MicroSequencer Reference Design
from Altera Corporation
Overview
The Altera® Avalon® MicroSequencer is a high-speed, low logic element (LE)-usage Avalon master with 32-bit data and address buses that employs a minimal instruction set to perform Avalon bus transfers as well as simple calculations. It can be used to control, initialize, and service peripherals in an Avalon system in applications that require extremely deterministic behavior. The Avalon MicroSequencer provides a solution where less logic and functionality than a microprocessor is required, as well as in time-critical designs where engineering a custom state machine would excessively increase time-to-market.
The Avalon MicroSequencer works by stepping through 36-bit microcode stored in internal synchronous ROM implemented using Stratix®, Cyclone®, or Cyclone II embedded RAM blocks. The 36-bit instruction word consists of a 4-bit opcode and a 32-bit immediate data field. The size of the instruction ROM is configurable (up to 64K of instruction words) in the component’s SOPC Builder Wizard.
Features
- Supports 16 instructions with 32-bit data field
- Small size 135 LEs or 270 LEs
- Configurable with or without an accumulator
Demonstrated Altera Technology
Block Diagram
Figure 1. Block Diagram
Reference Designs Disclaimer
These reference design illustrations may be used within Altera Corporation devices only and remain the copyrighted property of Altera. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
|
文档资料
> 
