CRC Hardware Acceleration Reference Design
from Altera Corporation
OverviewThe cyclic redundancy check (CRC) algorithm detects the corruption of data during transmission. It detects a higher percentage of errors than a simple checksum. The CRC calculation consists of an iterative algorithm involving XORs and shifts that execute much faster in hardware than in software. This design uses the CRC-32 standard. It is implemented as both a custom instruction and a custom component alongside a Nios® II embedded processor. The design achieves over 5 Gbps throughput, demonstrating the levels of performance improvement that can be achieved by performing the function in hardware. Features- Supports any CRC algorithm between 1–128 bits
- CRC component throughput of 32 Mbps/MHz
- 8-, 16-, 24-, and 32-bit datapaths
- Up to 2000x speed improvement over a software-only implementation
- Low latency performance of 0 cycle write latency and 1 cycle read latency
- Two reference designs targeting Stratix® II and Cyclone® II devices
Demonstrated Altera TechnologyBlock DiagramFigure 1 shows the Avalon® CRC component block diagram. Figure 1. Avalon CRC Component Block Diagram 
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Note: - Data path = crc_width.
Reference Designs DisclaimerThese reference design illustrations may be used within Altera Corporation devices only and remain the copyrighted property of Altera. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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