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Overview
Channel estimation and equalization are required at the base station to compensate for the deleterious effects of the wireless channel. The 802.16e-2005 standard specifies the use of pilot subcarriers to aid in the channel estimation process. Altera’s reference design demonstrates how you can efficiently implement these functions in Stratix® and Arria® series FPGAs. You can use the reference design as a starting point to accelerate designs based on the 802.16e-2005 standard. Altera supplies the reference design as DSP Builder-based design files.
Features
- Channel estimation based on two-dimensional coherent linear interpolation
- Interpolation in both time and frequency domain across all three uplink partial usage of subchannel (PUSC) symbols within the slot boundary
- Estimation mean squared error of less than -35 dB for the universal mobile telecommunication system (UMTS) vehicular channel at 120 kph
- Frequency domain zero-forcing equalization
- Single tap operation
- Performance in the range of approximately 2 dB compared to the ideal estimate of the UMTS vehicular channel at 120 kph
- Bit error rate of 0.01 at Eb/N0 of 17.5 dB for QPSK subcarrier mapping
- DSP Builder-based design methodology enables easy modifications to the design
Demonstrated Altera Technology
Block Diagram
Figure 1. Advanced Uplink Receiver Functions
Related Links
Reference Designs Disclaimer
These reference design illustrations may be used within Altera Corporation devices only and remain the copyrighted property of Altera. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
