High-Performance EMIF Bridge Core Reference Design
from Altera Corporation
OverviewThe high-performance EMIF bridge core reference design provides a connection between an Altera FPGA and the external memory interface (EMIF) of Texas Instruments (TI) TMS320C64x family of digital signal processors. The EMIF bridge core decodes external EMIF accesses and converts and forwards those accesses to the appropriate internal FPGA resource. Both digital signal processing (DSP) memory accesses and direct memory access (DMA) transfer operations are supported. The reference design is supplied with Verilog HDL. Features- Supports synchronous operation up to 133 MHz delivering new data every cycle
- Configurable as either EMIF A (32-bit or 64-bit data width) or EMIF B (16-bit width only)
- High-speed interface for developing FPGA co-processor systems
Demonstrated Altera TechnologyBlock DiagramAtlantic™ interfaces connect the FIFO buffers between the bridge and the internal application specific function. One FIFO buffer provides a read path and the other a write path to the internal FPGA function. The bridge Avalon® interface provides access to the configuration registers in the FIFO buffers. The Avalon interface can connect to any internal resource that has an Avalon interface via an Avalon bus module. Figure 1 shows a high-level block diagram of the reference design. Figure 1. High-Performance EMIF Bridge Core Block Diagram 
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