Farrow-Based Decimating Sample Rate Converter
from Altera Corporation
This reference design is supplied with the DSP Builder.
Download the latest version of DSP Builder. OverviewThe Farrow-based decimating sample rate converter demonstrates a Farrow resampler. You can simulate its performance in MATLAB, change it as required for your application, generate a VHDL version and synthesize it to Altera®devices. The converter is designed for an input clock rate identical to the system clock. For applications where the input rate is much lower than the system clock, time sharing should be implemented to get a cost-effective solution. The DSP Builder example file is FarrowResamp.mdl. Many integrated systems, such as software defined radios (SDR), require data to be resampled so that a unit can comply with different communication standards, where the sample rates are different. In some cases, where one clock rate is a simple integer multiple of another clock rate, resampling can be accomplished using interpolating and decimating finite impulse response (FIR) filters. However, in most cases the interpolation and decimation factors are so high that this approach is impractical. Farrow resamplers offer an efficient way to resample a data stream at a different sample rate. The underlying principle is that the phase difference between the current input and wanted output is determined on a sample-by-sample basis. This phasedifference is then used to combine the phases of apolyphase filter in such a way that a sample for the wanted output phase is generated. Demonstrated Altera TechnologyBlock DiagramFigure 1. Block Diagram 
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