from Altera Corporation
Please contact your local Altera sales representative for a copy of this reference design. The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Overview
As the LTE system partitioning diagram suggests, FPGAs are very well suited for bit rate processing in an LTE (or WiMAX) channel card application. Support for variable bandwidth and multiple sectors require the solution to be scalable. Altera’s LTE Turbo Decoder reference design is based on the 3GPP LTE specification and is designed for scalability. The solution is based on extensive systems analysis that provides the required throughput with a resource-efficient architecture and superior performance including bit-error rate (BER) and latency. This reference design was tested and validated against an extensive verification methodology. The solution also offers a choice of run-time and compile-time parameters.
Other deliverables that might also be of interest include:
- C/MATLAB bit-accurate models for performance simulation or register transfer level (RTL) test vector generation
- Generation of VHDL or Verilog HDL test benches using the MegaWizard® Plug-In Manager
OEMs can target this reference design for the following silicon platforms:
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These reference design illustrations may be used within Altera Corporation devices only and remain the copyrighted property of Altera. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
