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IBIS Models

The Ibis Altera® IBIS models are generated from HSPICE models, and are based on either IBIS version 2.1 or 3.2. All of the newer Altera device family models, such as Stratix® II GX, Stratix II, Stratix GX, Stratix, Hardcopy® II, Hardcopy Stratix, Cyclone® II, Cyclone, MAX® II, Mercury™, APEX™ II, APEX 20KC, and some APEX 20KE devices, are generated with IBIS version 3.2. The rest of the device models are generated with IBIS version 2.1. The IBIS models of Altera devices support the following features and characteristics:

Multi-Voltage Support

Altera devices support multiple voltages (VCCIO) and there are separate IBIS models for each of the supported voltages. To simplify the model identification and the corresponding voltage level, the following model names are used:

  • model_name_5 = 5.0-V VCCIO
  • model_name_3 or model_name_33 = 3.3-V VCCIO
  • model_name_2 or model_name_25 = 2.5-V VCCIO
  • model_name_1 or model_name_18 = 1.8-V VCCIO
  • model_name_15  = 1.5-V VCCIO

Slow Slew Rate Control

Most Altera devices have the option of turning the slew rate on and off. Files with an "s" or slew suffix in the signal/model name have the slew rate turned on. Likewise, files without an "s" or slew suffix have the slew rate turned off. For example:

  • model_name = slew rate off
  • model_name_s or model_name_slew  = slew rate on

PCI Clamp Diode

Most Altera devices have the option of turning the PCI clamp diode on and off. Files with "p" or pci suffix in the signal/model name have the PCI clamp-diode enabled. Likewise, files without a "p" or pci suffix have the PCI clamp-diode disabled. For example:

  • model_name = PCI clamp diode off
  • model_name_p or model_name_pci = PCI clamp diode on

PCI Clamp Diode and Slew Rate Control

Some Altera device models have both PCI clamp diode and slow slew rate control options enabled. Files with a "sp" in the signal/model name have both the PCI clamp diode and slew rate control options enabled. Likewise, files without a "sp" have both the PCI clamp diode and slew rate control options disabled. The following file name is the Stratix GX model with PCI clamp diode and slew rate control enabled:

  • 1sgx_ttl33_io_d12ps = Stratix GX device model with the PCI clamp diode and slew control rate option on

Corner Case Support

Altera IBIS models support all three corner cases: Typical, Minimum, and Maximum. Each corner is defined by its specific voltage, process, and temperature range. The corner case information is available within the Altera IBIS model.

Supported I/O Standards

Altera IBIS models support a variety of I/O standards, including:

  • 3.3-V LVTTL/ LVCMOS
  • 2.5-V LVTTL/ LVCMOS
  • 1.8-V LVTTL/ LVCMOS
  • 1.5-V LVCMOS
  • 1.2-V LVCMOS
  • SSTL-18
  • SSTL-2
  • SSTL-3
  • GTL+
  • HSTL-18
  • HSTL-15
  • HSTL-12 
  • 3.3-V PCI
  • 3.3-V PCI-X
  • 3.3-V PCML
  • LVDS
  • LVPECL
  • HyperTransport™ (HT)
  • CTT

Altera IBIS model names specify the supported I/O standard. The following examples show the I/O standard indication in the model name for several devices:

  • 2c_hstl18c2_cio_d18 represents a Cyclone II device model at column I/O bank with HSTL-18 class II standard
  • 1s_ttl33_io_d4 represents a Stratix device model with 3.3-V LVTTL standard
  • apex2_sstl2_in represents an APEX II device input model with 2.5-V SSTL-2 standard

Programmable Driver Current Strength

For newer Altera devices such as Stratix, the drivers have different current strengths at various VCCIO levels. To distinguish between models, each model name specifies the driver’s current strength, the VCCIO level, and the I/O standard. For example, apex2_ttl_18v_4ma_s model name specifies the following:

  • APEX II device model
  • LVTTL I/O driver
  • VCCIO = 1.8 V
  • Driver current strength = 4 mA
  • Slew rate control option on

Package RLC Values

Altera provides the package RLC values for each device family on the IBIS Models home page.

IBIS Output File Generation With Quartus II Software

Quartus® II software version 2.0 and later automatically generates an IBIS output file to perform board-level signal integrity verification using EDA tools. For more information on generating IBIS output files with Quartus II software, go to the Generating IBIS Files With Quartus page.

Related IBIS Links

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