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主页 > 支持 > 软件 > Using Cadence Composer & MAX+PLUS II Software 打印此页 发送此页 Using Cadence Composer & MAX+PLUS II Software The following topics describe how to use the Cadence Composer software with MAX+PLUS® II software. Click on one of the following topics for information: This file is suitable for printing only. It does not contain hypertext links that allow you to jump from topic to topic. Setting Up the MAX+PLUS II/Cadence Working Environment Software Requirements MAX+PLUS II Directory Structure MAX+PLUS II/Cadence Interface File Organization Composer Project File Directory Structure Altera-Provided Logic & Symbol Libraries Design Entry Design Entry Flow Creating Composer Schematics for Use with MAX+PLUS II Software Entering Resource Assignments Assigning Pins, Logic Cells & Chips Assigning Cliques Assigning Logic Options Modifying the Assignment & Configuration File with the setacf Utility Creating Hierarchical Projects in Composer Schematics Converting Composer Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the altout Utility Functional Simulation Performing a Functional Simulation of a Composer Schematic with Verilog-XL Software Related Topics: Compiling Projects with MAX+PLUS II Software Programming Altera Devices   Go to the following topics, which are available on the web, for additional information: MAX+PLUS II Development Software Altera Programming Hardware Cadence web site (http://www.cadence.com) Setting Up the MAX+PLUS II/Cadence Working Environment To use MAX+PLUS® II software with Cadence software, you must first install the MAX+PLUS II software, then establish an environment that facilitates entering and processing designs. The MAX+PLUS II/Cadence interface is installed automatically when you install the MAX+PLUS II software on your computer. Go to MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual for more information on installation and details on the directories that are created during MAX+PLUS II installation. Go to MAX+PLUS II/Cadence Interface File Organization for information about the MAX+PLUS II/Cadence directories that are created during MAX+PLUS II installation. The information presented here assumes that you are using the C shell and that your MAX+PLUS II system directory is /usr/maxplus2. If not, you must use the appropriate syntax and procedures to set environment variables for your shell. To set up your working environment for the MAX+PLUS II/Cadence interface, follow these steps: Ensure that you have correctly installed the MAX+PLUS II and Cadence software versions described in the MAX+PLUS II/Cadence Software Requirements. Add the following environment variables to your .cshrc file: setenv ALT_HOME /usr/maxplus2 setenv CDS_INST_DIR <Cadence system directory path> Add the $ALT_HOME/cadence/bin and $CDS_INST_DIR/tools/bin directories to the PATH environment variable in your .cshrc file. Make sure these paths are placed before the Cadence hierarchy path. Add /usr/dt/lib and /usr/ucb/lib to the LD_LIBRARY_PATH environment variable in your .cshrc file. Create a new cds.lib file in your working directory or edit an existing one so that it includes all of the following lines that apply to the Cadence tools you have installed: DEFINE alt_syn ${ALT_HOME}/simlib/concept/alt_syn DEFINE lpm_syn ${ALT_HOME}/simlib/concept/lpm_syn DEFINE alt_lpm ${ALT_HOME}/simlib/concept/alt_lpm DEFINE alt_mf ${ALT_HOME}/simlib/concept/alt_mf DEFINE alt_max2 ${ALT_HOME}/simlib/concept/alt_max2 DEFINE alt_max2 ${ALT_HOME}/simlib/composer/alt_max2/alt_max2 DEFINE alt_vtl $ALT_HOME/simlib/concept/alt_vtl/lib DEFINE altera $ALT_HOME/simlib/concept/alt_mf/lib SOFTINCLUDE $CDS_INST_DIR/tools/leapfrog/files/cds.lib DEFINE <design name>. Copy the /usr/maxplus2/maxplus2.ini file to your $HOME directory: cp /usr/maxplus2/maxplus2.ini $HOME chmod u+w $HOME/maxplus2.ini The maxplus2.ini file contains both Altera- and user-specified initialization parameters that control the MAX+PLUS II software, such as MAX+PLUS II symbol and logic function library paths and the current project name. The MAX+PLUS II installation procedure creates and copies the maxplus2.ini file to the /usr/maxplus2 directory. Normally, you do not have to edit your local copy of maxplus2.ini because the MAX+PLUS II software updates the file automatically whenever you change any parameters or settings. However, if you move the max2lib and max2inc library subdirectories, you must update the file. Go to "Creating & Using a Local Copy of the maxplus2.ini File" in MAX+PLUS II Help for more information. If you are using Concept on a Sun SPARCstation running SunOS, go to Setting Up the MAX+PLUS II/Cadence Concept Work Environment for a Sun SPARCstation Running SunOS Software to install the redifnet EDIF netlist reader utility. If you are using Synergy software, edit the hdl.var file located in your working directory to include the following line: DEFINE work <design name> Set up an appropriate directory structure for the tool(s) you are using. See the following topics for information: Composer Project File Directory Structure Concept & RapidSIM Local Work Area Directory Structure Related Topics: MAX+PLUS II Getting Started version 8.1 (5.4 MB) This manual is also available in 4 parts: Preface & Section 1: MAX+PLUS II Installation Section 2: MAX+PLUS II - A Perspective Section 3: MAX+PLUS II Tutorial Appendices, Glossary & Index MAX+PLUS II Directory Structure In the MAX+PLUS® II software, a project name is the name of a top-level design file, without the filename extension. This design file can be an EDIF, Verilog HDL, or VHDL netlist file; an AHDL Text Design File (TDF); or any other MAX+PLUS II-supported design file. The EDIF netlist file must be created by the altout or concept2alt utility and imported into the MAX+PLUS II software as an EDIF Input File (.edf). Project design files and output files are stored in the project directory, with the exception of standard library functions provided by Altera or another EDA tool vendor. The MAX+PLUS II software stores the connectivity data on the links between design files in a hierarchical project in a Hierarchy Interconnect File (.hif), but refers to the entire project only by its project name. The MAX+PLUS II Compiler uses the HIF to build a single, fully flattened project database that integrates all design files in a project hierarchy. MAX+PLUS II/Cadence Interface File Organization Table 1 shows the MAX+PLUS® II/Cadence interface subdirectories that are created in the MAX+PLUS II system directory (by default, the /usr/maxplus2 directory) during MAX+PLUS II installation. For information on the other directories that are created during MAX+PLUS II installation, see "MAX+PLUS II File Organization" in MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual. Table 1. MAX+PLUS II Directory Organization Directory Description ./lmf Contains the Altera-provided Library Mapping File, cadence.lmf, that maps Cadence logic functions to equivalent MAX+PLUS II logic functions. ./examples/cadence Contains the sample files for Cadence software discussed in these ACCESSSM Key Guidelines. ./cadence Contains the AMPLE userware for the MAX+PLUS II/Cadence interface. ./simlib/concept/alt_max2 Contains the MAX+PLUS II primitives, including CARRY, CASCADE, EXP, GLOBAL, LCELL, SOFT, OPNDRN, DFFE (D flipflop with Clock Enable), and DFFE6K (D flipflop with Clock Enable and both Clear and Preset for FLEX® 6000 devices only) for use with Concept software. ./simlib/composer/alt_max2 Contains the MAX+PLUS II primitives, including CARRY, CASCADE, EXP, GLOBAL, LCELL, SOFT, OPNDRN, DFFE (D flipflop with Clock Enable), and DFFE6K (D flipflop with Clock Enable and both Clear and Preset for FLEX 6000 devices only) for use with Composer software. ./simlib/concept/alt_lpm Contains the MAX+PLUS II megafunctions, including library of parameterized modules (LPM) functions, for use with Concept software. ./simlib/concept/max2sim Contains the MAX+PLUS II/Concept simulation model library, max2_sim, for use with RapidSIM software. ./simlib/concept/alt_syn Contains the MAX+PLUS II synthesis library, alt_syn, for use with Synergy and Concept software, and the vlog2alt utility. ./simlib/composer/alt_syn Contains the MAX+PLUS II synthesis library, alt_syn, for use with Synergy and Composer software. ./simlib/concept/lpm_syn Contains the Cadence LPM library, lpm_syn, for use with Synergy and Concept software. ./simlib/composer/lpm_syn Contains the Cadence LPM library, lpm_syn, for use with Synergy and Composer software. ./simlib/concept/alt_mf Contains the MAX+PLUS II VHDL logic function library. (a_8count is for the MAX® 7000 and MAX 9000 device families only.) ./simlib/concept/edifnet/templates Contains template files for Concept directives, i.e., global.cmd, compiler.cmd, vloglink.cmd, verilog.cmd, and master.local. ./simlib/concept/alt_max2/verilogUdps Contains Verilog HDL modules that are the equivalent of the primitives contained in alt_max2 library for use with Concept software. ./simlib/composer/alt_max2/verilogUdps Contains Verilog HDL modules that are the equivalent of the primitives contained in alt_max2 library for use with Composer software. ./simlib/concept/alt_vtl ./simlib/composer/alt_vtl Contains VITAL library source files for use with Concept or Composer software. ./simlib/composer/alt_max2/verilog Contains simulation modules for all symbols in the alt_max2 Composer library. Related Topics: MAX+PLUS II Getting Started version 8.1 (5.4 MB) This manual is also available in 4 parts: Preface & Section 1: MAX+PLUS II Installation Section 2: MAX+PLUS II - A Perspective Section 3: MAX+PLUS II Tutorial Appendices, Glossary & Index FLEX Devices MAX Devices Classic Device Family Composer Project File Directory Structure The Composer software generates the following files for each schematic (where x represents a Composer-generated number): <drawing name>_x/schema_59.0_x <drawing name>_x/schema_59.0_x% Altera-Provided Logic & Symbol Libraries The MAX+PLUS® II/Cadence environment provides four logic and symbol libraries that are used for compiling, synthesizing, and simulating designs. You can create your own libraries of custom symbols and logic functions in Concept and Composer. You can use custom symbols to incorporate an EDIF Input File, Text Design File (TDF), or any other MAX+PLUS II-supported design file into a project. MAX+PLUS II uses the cadence.lmf Library Mapping File to map standard Concept or Composer symbols to equivalent MAX+PLUS II logic functions. To use custom symbols, you can create a custom LMF that maps your custom symbols to the equivalent MAX+PLUS II-supported design file. You must also specify the directory that contains the MAX+PLUS II-supported design file(s) as a user library with the MAX+PLUS II User Libraries command (Options menu). Go to "Library Mapping File" and "Cadence Library Mapping File (cadence.lmf)" in MAX+PLUS II Help for more information. The alt_max2 Library You can enter a Concept or Composer Design Architect schematic with primitives and macrofunctions from the Altera-provided symbol library alt_max2. The alt_max2 library includes 74-series macrofunctions and several MAX+PLUS II primitives with corresponding Verilog HDL simulation models for controlling design synthesis and fitting. It also includes four macrofunctions--a_8count, a_8mcomp, a_8fadd, and a_81mux--that are optimized for different device families, and the clklock phase-locked loop megafunction, which is supported by some FLEX® 10K devices, with corresponding Verilog HDL and VHDL simulation models. See Table 1. Choose Old-Style Macrofunctions and/or Primitives from the MAX+PLUS II Help menu for more information on functions in the alt_max2 library. The alt_lpm Library The Altera-provided alt_lpm library, which is available for Concept and Verilog HDL designs, includes standard functions from the library of parameterized modules (LPM) 2.1.0, except the truth table, finite state machine, and pad functions. Other parameterized functions, including cycle-shared FIFO (csfifo) and cycle-shared dual-port RAM (csdpram) are also included. The LPM standard defines a set of parameterized modules (i.e., parameterized megafunctions) and their corresponding representations in an EDIF netlist file. These logic functions allow you to create and functionally simulate an LPM-based design without targeting a specific device family. The parameters you specify for each LPM function determine the simulation models that will be generated. After the design is completed, you can target the design to any device family. In designs created with Concept, the Altera alt_lpm library works only with HDL Direct and the hdlconfig utility. Choose Megafunctions/LPM from the MAX+PLUS II Help menu for more information about LPM functions in the alt_lpm library. The lpm_syn Library The lpm_syn library contains the Altera-provided parameterized functions. The lpm_syn library is similar to the alt_lpm library, except that it contains VHDL and Verilog HDL logic functions for use with Synergy, Concept, and Composer software. The alt_mf Library Altera provides a VHDL logic function library, alt_mf, that currently includes four macrofunctions--a_8count, a_8mcomp, a_8fadd, and a_81mux--for controlling design synthesis and fitting. These elements can be instantiated directly in your VHDL file. To designate that these logic functions should pass untouched through the EDIF netlist file to the MAX+PLUS II Compiler, you must select the Maintain attribute constraint for instances of these functions before running the Synergy software. These models allow you to perform functional VHDL simulation while maintaining an architecture-independent VHDL description. Table 1 shows the MAX+PLUS II-specific logic functions. Table 1. MAX+PLUS II-Specific Logic Functions Macrofunctions Note (1) Primitives Name Description Name Description Name Description 8fadd 8-bit full adder LCELL Logic cell buffer EXP MAX® 5000, MAX 7000, and MAX 9000 Expander buffer 8mcomp 8-bit magnitude comparator GLOBAL Global input buffer SOFT Soft buffer 8count Note (2) 8-bit up/down counter CASCADE FLEX 6000, FLEX 8000, and FLEX 10K cascade buffer OPNDRN Open-drain buffer 81mux 8-to-1 multiplexer CARRY FLEX 6000, FLEX 8000, and FLEX 10K carry buffer DFFE DFFE6K Note (3) D-type flipflop with Clock Enable clklock Phase-locked loop Notes: Logic function names that begin with a number must be preceded by "a_" in VHDL designs. For example, 8fadd must be specified as a_8fadd. The a_8count logic function is for the MAX 7000 and MAX 9000 device families only. For designs that are targeted to FLEX 6000 devices, you should use the DFFE primitive only if the design contains either a Clear or Preset signal, but not both. If your design contains both a Clear and a Preset signal, you must use the DFFE6K primitive. Related Topics: FLEX Devices MAX Devices Classic Device Family Cadence Design Entry Flow Figure 1 shows the design entry flow for the MAX+PLUS® II/Cadence interface. Figure 1. MAX+PLUS II/Cadence Design Entry Flow Altera-provided items are shown in blue. Creating Composer Schematics for Use with MAX+PLUS II Software You can create Composer schematics and convert them into EDIF Input Files (.edf) that can be processed with the MAX+PLUS® II Compiler. To create a Composer schematic for use with the MAX+PLUS II software, follow these steps: Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment. Start the Composer schematic editor from the <working directory> by typing icds at a UNIX prompt. Use the graphical user interface to structure and organize your files to create an environment that facilitates entering and processing designs. Go to Composer Project File Directory Structure for more information on directories in Composer. Choose Library Path Editor (Tools menu) to create the <design name> library. In the Library dialog box, type <project directory name> as the Library name and ./source/<design name> as the Path name. Choose Save (File menu), then choose Exit (File menu) to save the path. Choose Library Manager (Tools menu) to start Composer and create a new design. Type <project directory name> as the Library name, <design name> as the Cell name, and schematic as the View name in the Library Manager dialog box and press the key. Enter primitives, megafunctions, and macrofunctions from the following libraries: MAX+PLUS II-compatible primitives, megafunctions, and macrofunctions are available in the Altera-provided alt_max2 component library. Input, output, and bidirectional pins are available in the Cadence basic library located under /cadence/etc/cdslib. MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support. If you wish to create a hierarchical design that contains symbols representing other design files, such as Altera® Hardware Description Language (AHDL) Text Design Files, go to Creating Hierarchical Projects in Composer Schematics. Enter meaningful instance names for all symbols and functions so that you can easily trace internal node names during simulation and debugging operations. For example, if an a161 macrofunction is instantiated several times in one design, you should define a unique name for each instance. The instance name for each symbol is controlled by INST property. For more information on assigning properties, refer to the Cadence Composer User Guide. (Optional) To enter resource assignments in your Composer schematic, go to Entering Resource Assignments. You can also enter resource assignments from within the MAX+PLUS II software. (Optional) Functionally simulate the design with the Verilog-XL simulator. Altera provides Verilog HDL simulation modules in the /usr/maxplus2/simlib/composer/alt_max2/verilog and /usr/maxplus2/simlib/composer/alt_max2/verilogUdps directories. Go to Performing a Functional Simulation of a Composer Schematic with Verilog-XL Software for more information. Use the altout utility to generate an EDIF netlist file that can be imported into the MAX+PLUS II software, as described in Converting Composer Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the altout Utility. Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software. Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample Composer schematic files: /usr/maxplus2/examples/cadence/example2/fulladd /usr/maxplus2/examples/cadence/example5/fulladd2 /usr/maxplus2/examples/cadence/example7/fa2 Entering Resource Assignments The MAX+PLUS® II software allows you to enter a variety of resource and device assignments for your projects. Resource assignments are used to assign logic functions to a particular pin, logic cell, I/O cell, embedded cell, row, column, Logic Array Block (LAB), Embedded Array Block (EAB), chip, clique, local routing, logic option, timing requirement, or connected pin group. In MAX+PLUS II software, you can enter all types of resource and device assignments with Assign menu commands. You can also enter pin, logic cell, I/O cell, embedded cell, LAB, EAB, row, and column assignments in the MAX+PLUS II Floorplan Editor. The Assign menu commands and the Floorplan Editor all save assignment information in the ASCII Assignment & Configuration File (.acf) for the project. In addition, you can edit ACFs manually in any standard text editor or with the setacf utility. Concept & Composer Schematics In both Concept and Composer schematics, you can assign a limited subset of these resource assignments by assigning properties to symbols. These properties are incorporated into the EDIF netlist file(s). The MAX+PLUS II software automatically converts assignment information from the EDIF Input File into the ACF format. For information on making MAX+PLUS II-compatible resource assignments, go to the following topics: Assigning Pins, Logic Cells & Chips Assigning Cliques Assigning Logic Options Modifying the Assignment & Configuration File with the setacf Utility Go to the Cadence Concept Schematic User Guide and Composer Reference User Guide for details on how to assign properties. Go to "Resource Assignments in EDIF Input Files" and "Assigning Resources in a Third-Party Design Editor" in MAX+PLUS II Help for more information on assignments or properties that can be assigned in Concept and Composer. Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample Concept and Composer schematic files, which include resource assignments: /usr/maxplus2/examples/cadence/example6/fa2 (Concept) /usr/maxplus2/examples/cadence/example7/fa2 (Composer) VHDL & Verilog HDL Design Files For Verilog HDL- and VHDL-based designs, you must use the MAX+PLUS II software or the setacf utility to enter resource assignments. For information on using the setacf utility, go to Modifying the Assignment & Configuration File with the setacf Utility. For information on entering assignments in the MAX+PLUS II software with Assign menu commands or in an ACF, go to "resource assignments" or "ACF, format" in MAX+PLUS II Help using Search for Help on (Help menu). Assigning Pins, Logic Cells & Chips You can assign a single logic function to a specific pin or logic cell (including I/O cells and embedded cells) within a chip, and assign one or more functions to a specific chip. A chip is a group of logic functions defined as a single, named unit, which can be assigned to a specific device. You can assign a signal to a particular pin to ensure that the signal is always associated with that pin, regardless of future changes to the project. If you wish to set and maintain the performance of your project, assigning logic to a specific logic cell within a chip can minimize timing delays. In a project that is partitioned among multiple devices, you can assign logic functions that must be kept together in the same device to a chip. Chip assignments allow you to split a project so that only a minimum number of signals travel between devices, and to ensure that no unnecessary device-to-device delays exist on critical timing paths. You can assign a chip to a device in some EDA tools or in the MAX+PLUS® II software. Use the following syntax for chip, pin, and logic cell assignments: To assign a logic function to a chip: CHIP_PIN_LC=<chip name> For example: CHIP_PIN_LC=chip1 To assign a pin number within a chip: CHIP_PIN_LC=<chip name>@<pin number> For example: CHIP_PIN_LC=chip1@K2 To assign a logic cell, I/O cell, or embedded cell number: CHIP_PIN_LC=<chip name>@LC<logic cell number> CHIP_PIN_LC=<chip name>@IOC<I/O cell number> CHIP_PIN_LC=<chip name>@EC<embedded cell number> For example: CHIP_PIN_LC=chip1@LC44 Related Topics: Go to "Devices & Adapters" and "Assigning a Device" in MAX+PLUS II Help for information on device pin-outs and assigning devices, respectively, in the MAX+PLUS II software. Go to Back-Annotating MAX+PLUS II Pin Assignments to Design Architect Symbols for information on back-annotating pin assignments in Mentor Graphics Design Architect schematics.

Assigning Cliques

You can define a group of logic functions as a single, named unit, called a clique. The MAX+PLUS^® II Compiler attempts to place all logic in the clique in the same logic array block (LAB) to ensure optimum speed. If the project does not use multi-LAB devices, or if it is not possible to fit all clique members into a single LAB, the clique assignment ensures that all members of a clique are placed in the same device. In FLEX^® 6000, FLEX 8000, FLEX 10K, and MAX^® 9000 devices the Compiler also attempts to place the logic in LABs in the same row. Cliques therefore allow you to partition a project so that only a minimum number of signals travel between LABs, and to ensure that no unnecessary LAB-to-LAB or device-to-device delays exist on critical timing paths.

To assign a clique, use the following syntax: CLIQUE=<clique name> For example: CLIQUE=fast1

Related Topics:

Guidelines for Achieving Maximum Speed Performance

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Assigning Logic Options

Logic option and logic synthesis style assignments allow you to guide logic synthesis with logic optimization features that are specific to Altera^® devices. You can assign logic options and styles to individual logic functions in your design. The MAX+PLUS^® II Compiler also uses a device-family-specific default logic synthesis style for each project.

Related Topics:

• Go to "Resource Assignments in EDIF Input Files" and "Assigning Resources in a Third-Party Design Editor" in MAX+PLUS II Help for complete and up-to-date information on logic option and logic synthesis style assignments, including definitions and syntax of these assignments.

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Modifying the Assignment & Configuration File with the setacf Utility

Altera provides the setacf utility to help you modify a project's Assignment & Configuration File (.acf) from the command line, without opening the file with a text editor. Type setacf -h at a UNIX or DOS prompt to get help on this utility.

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Creating Hierarchical Projects in Composer Schematics

If you wish to create a hierarchical design that contains symbols representing other design files, such as Altera^® Hardware Description Language (AHDL) Text Design Files (.tdf), you can create a hollow-body symbol that represents a design file and then instantiate it in your Composer schematic.

To create a hierarchical project in your Composer schematic, follow these steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS^® II/Cadence Working Environment.

2. Create a Composer schematic and save it in your working directory, as described in Creating Composer Schematics for Use with MAX+PLUS II Software.
   
   

   You can instantiate MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.

3. Create the hollow-body symbol <design name> in Composer by typing icds from the <working directory> at the UNIX prompt.

4. Choose Library Path Editor (Tools menu) to create the <design name> library. Type <design name> as the Library name and ./source/<design name> as the Path name. Choose Save (File menu), then choose Exit (File menu) to save the path and exit from the Library Path Editor.

5. Choose Library Manager (Tools menu) to start Composer and create a symbol for your design. Type <project directory name> as the Library name, <lower-level design name> as the Cell name, symbol as the View name, and then press .

6. Create a hollow-body symbol that represents the inputs and outputs of your design.

7. Enter input and output pins for the symbol.

8. Save the symbol.

9. To enter the symbol in your higher-level schematic design, choose the Component button and type <project directory name> as the Library name, <lower-level design name> as the Cell name, and symbol as the View name.

10. The MAX+PLUS II software uses the cadence.lmf Library Mapping File to map Concept symbols to equivalent MAX+PLUS II logic functions. To use custom symbols, you must create a custom LMF that maps your custom symbols to the equivalent EDIF Input File, Text Design File (TDF), or other design file. You will also need to specify this custom LMF in the EDIF Netlist Reader Settings dialog box before compiling with the MAX+PLUS II software. See Compiling Projects with MAX+PLUS II Software for more information.

11. Continue with the steps necessary to complete your Composer schematic, as described in Creating Composer Schematics for Use with MAX+PLUS II Software.

Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample hierarchical AHDL and Composer schematic file:

• /usr/maxplus2/examples/cadence/example5/fulladd2

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Converting Composer Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the altout Utility

You can use the altout utility to generate an EDIF netlist file from a Composer schematic. This file can then be imported into the MAX+PLUS^® II software as an EDIF Input File (.edf).

To convert Composer schematics into MAX+PLUS II-compatible EDIF netlist files, follow these steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment.

2. Create a Composer schematic and save it in your working directory, as described in Creating Composer Schematics for Use with MAX+PLUS II Software.
   
   

   You can instantiate MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.

   
   

3. Type the following command at the UNIX prompt from the working directory that contains the schematic:

   altout -lib <design name> -rundir max2 <design name>

4. Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.

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Performing a Functional Simulation of a Composer Schematic with Verilog-XL Software

You can perform a functional simulation of a Cadence Composer schematic with the Verilog-XL simulator before compiling your project with the MAX+PLUS^® II software.

To functionally simulate a Composer schematic, follow these steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the
   MAX+PLUS II/Cadence Working Environment.

2. Create a Composer schematic and save it in your working directory, as described in Creating Composer Schematics for Use with MAX+PLUS II Software.

3. In Composer, select Simulation from the Tools drop-down list.

4. Select Verilog-XL to start the Verilog-XL Integration Control window.

5. When you are ready to compile the project, generate an EDIF netlist file <design name>.edf with the altout utility, as described in Converting Composer Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the altout Utility.

6. Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.

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Compiling Projects with MAX+PLUS II Software

The MAX+PLUS^® II Compiler can process design files in a variety of formats. This topic describes how to use MAX+PLUS II software to compile projects in which the top-level design file is an EDIF Input File (with the extension .edf).

Related Topics:

• Go to MAX+PLUS II Help for information on compiling VHDL and Verilog HDL, design files directly with the MAX+PLUS II Compiler.

• Go to Running Synopsys Compilers from MAX+PLUS II Software for information on running the Synopsys Design Compiler or FPGA Compiler software on a VHDL or Verilog HDL design from within the MAX+PLUS II Compiler window.

To compile a design (also called a "project") with MAX+PLUS II software, go through the following steps:

1. Create design files that are compatible with the MAX+PLUS II software and convert them into EDIF Input Files with the extension .edf. Specific instructions for some tools are described in these MAX+PLUS II ACCESS^SM Key Guidelines. Otherwise, refer to MAX+PLUS II Help or the product documentation for your design entry or synthesis and optimization tool.

2. If your design files contain symbols (or HDL instantiations) representing your own custom lower-level logic functions, create a mapping for each function in a Library Mapping File (.lmf) to map the custom symbol to the corresponding EDIF Input File, AHDL Text Design File (.tdf), or other MAX+PLUS II-supported design file. These custom functions are represented in design files as hollow-body symbols or "black box" HDL descriptions.

   Go to "Library Mapping Files (.lmf)" in MAX+PLUS II Help for more information.

3. Open MAX+PLUS II and specify the name of your top-level design file as the project name with the Project Name command (File menu). If you open an HDL file in the MAX+PLUS II Text Editor, you can choose the Project Set Project to Current File command (File menu) instead.

   You can also compile a project from a command line. However, the first time you compile a project, the settings you need to specify are easier to specify from within the MAX+PLUS II software. After you have run the graphical user interface for the MAX+PLUS II software at least once, you can more easily use the command-line setacf utility to modify options in the Assignment & Configuration File (.acf) for the project. Type setacf -h  and maxplus2 -h for descriptions of setacf and MAX+PLUS II command-line syntax.

4. Choose Device (Assign menu) and select the target Altera device family in the Device Family drop-down list box. If you wish to implement the design logic in a specific device, select it in the Devices box. Otherwise, select AUTO to allow the MAX+PLUS II Compiler to choose the best device(s) in the current device family. If your design entry or synthesis and optimization tool required you to specify a target family and/or device, specify the same information in this dialog box. For information on partitioning logic among multiple devices, go to MAX+PLUS II Help. Choose OK.

5. Open the Compiler window by choosing the Compiler command (MAX+PLUS II menu). Go through the following steps to specify the options necessary to compile the design file(s) in your project:

   1. Ensure that all EDIF netlist files have the extension .edf and choose EDIF Netlist Reader Settings (Interfaces menu).

   2. Select a vendor name in the Vendor drop-down list box to activate the default settings for that vendor. This name should be the name of the vendor whose tool(s) you used to create the EDIF netlist files. If your vendor name does not appear, select Custom instead.

      If you are compiling a design created with Synopsys FPGA Express software, select Synopsys, choose the Customize button, enter <project name>.lmf in the LMF #1 box, choose OK, and skip to step 6.

   3. If you selected an existing vendor name in the Vendor box and your project contains design files that require custom LMF mappings, choose the Customize button to expand the dialog box to show all settings. Turn on the LMF #2 checkbox and type your custom LMF's filename in the corresponding text box, or select a name from the Files box. The selection in the Vendor box will change to Custom and all settings will be retained until you change them again.

   4. If you selected Custom in the Vendor box, choose the Customize button to expand the dialog box to show all settings. Any previously defined custom settings will be displayed. Under Signal Names, type one or more names with up to 20 total name characters in the VCC or GND box if your EDIF Input File(s) use one or more names other than VCC or GND for the global high or low signals. Multiple signal names must be separated by either a comma (,) or a space. Under Library Mapping Files, turn on the LMF #1 checkbox and type a filename in the text box following it, or select a name from the Files box. If necessary, specify another LMF name in the LMF #2 box. Go to MAX+PLUS II Help for detailed information on the settings available in the EDIF Netlist Reader Settings dialog box.

   5. Choose OK.

6. If your design files contain symbols (or HDL instantiations) representing your own custom lower-level logic functions, you may need to ensure that all files are present in your project directory, i.e., the same directory as the top-level design file. Otherwise, you must specify the directories containing these files as user libraries with the User Libraries command (Options menu).

7. Follow all guidelines that apply to your design entry or synthesis and optimization tool:
   • Exemplar Logic Galileo Extreme-Specific Compiler Settings
   • Synopsys DesignWare-Specific Compiler Settings
   • Converting Synopsys FPGA Compiler & Design Compiler Timing Constraints into MAX+PLUS II-Compatible Format with the syn2acf Utility
   • Synplicity Synplify-Specific Compiler Settings

8. If you wish to generate EDIF, VHDL, or Verilog HDL output files for post-compilation simulation or timing analysis with another EDA tool, go through the following steps:

   1. (Optional) Turn on the Optimize Timing SNF command (Processing menu) to reduce the size of the output file(s). Turning on this command can reduce the size of output netlists by up to 30%.

      This command does not create optimized timing SNFs on UNIX workstations. However, a non-optimized timing SNF provides the same functional and timing information as an optimized timing SNF.

   2. If you wish to generate EDIF Output Files (.edo), go through these steps:

      1. Turn on the EDIF Netlist Writer command (Interfaces menu). Then choose the EDIF Netlist Writer Settings command (Interfaces menu).

      2. Select a vendor name in the Vendor drop-down list box to activate the default settings for that vendor and choose OK. If your vendor name does not appear, select Custom instead and specify the settings that are appropriate for your simulation or timing analysis tool. Go to MAX+PLUS II Help for detailed information on the options available in the EDIF Netlist Writer Settings dialog box.

      3. To generate an optional Standard Delay Format (SDF) Output File (.sdo), choose the Customize button to expand the dialog box to show all settings. Select one of the SDF Output File options under Write Delay Constructs To, and choose OK.

      The filenames of the EDIF Output File(s) and optional SDF Output File(s) are the same as the user-defined chip name(s) for the project; if no chip names exist, the Compiler assigns filenames that are based on the project name. For a multi-device project, the Compiler also generates a top-level EDIF Output File that is uniquely identified by "_t" appended to the project name. In addition, the Compiler automatically generates a VHDL Memory Model Output File, <project name>.vmo, when it generates an EDIF Output File that contains memory (RAM or ROM).

   3. If you wish to generate VHDL Output Files (.vho), turn on the VHDL Netlist Writer command (Interfaces menu). Then choose VHDL Netlist Writer Settings command (Interfaces menu). Select VHDL Output File (.vho) or one of the SDF Output File options under Write Delay Constructs To, and choose OK. SDF ver. 2.1 files contain timing delay information that allows you to perform back-annotation simulation in VHDL with VITAL-compliant simulation libraries. The VHDL Output Files generated by the Compiler have the extension .vho, but are otherwise named in the same way as the EDIF Output Files described above.

   4. If you wish to generate Verilog HDL Output Files (.vo), turn on the Verilog Netlist Writer command (Interfaces menu). Then choose Verilog Netlist Writer Settings command (Interfaces menu). Select Verilog Output File (.vo) or one of the SDF Output File options under Write Delay Constructs To, and choose OK. SDF Output Files contain timing delay information that allows you to perform back-annotation simulation in Verilog HDL. The Verilog Output Files generated by the Compiler have the extension .vo, but are otherwise named in the same way as the EDIF Output Files described above.

9. To run the MAX+PLUS II Compiler, choose the Project Save & Compile command (File menu) or choose the Start button in the Compiler window.

   See step 3 for information on running MAX+PLUS II software from the command line.

10. Once you have compiled the project with the MAX+PLUS II Compiler, you can use the VHDL, Verilog HDL, or EDIF output file(s), and the optional SDF Output File(s) (.sdo) to perform timing analysis or timing simulation with another EDA tool. Specific instructions for some tools are described in these MAX+PLUS II ACCESS Key Guidelines. Otherwise, refer to MAX+PLUS II Help or the product documentation for your EDA tool.

The MAX+PLUS II Compiler also generates a Report File (.rpt), a Pin-Out File (.pin), and one or more of the following files for device programming or configuration:

• JEDEC Files (.jed)
• Programmer Object Files (.pof)
• SRAM Object Files (.sof)
• Hexadecimal (Intel-format) Files (.hex)
• Tabular Text Files (.ttf)

Related Topics:

• Go to Compiler Procedures in MAX+PLUS II Help for information on other available Compiler settings.
• Go to Programmer Procedures in MAX+PLUS II Help for instructions on creating other types of programming files and on programming or configuring Altera devices.
• Go to Back-Annotating MAX+PLUS II Pin Assignments to Design Architect Symbols for information on back-annotating pin assignments in Mentor Graphics Design Architect schematics.
• Go to Programming Altera Devices for information on the different programming hardware options for Altera device families.

	Go to the following topics, which are available on the web, for additional information:
	MAX+PLUS II Development Software Altera Programming Hardware

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Programming Altera Devices

Once you have successfully compiled and simulated a project with the MAX+PLUS^® II software, you can program an Altera^® device and test it in the target circuit. Figure 1 shows the device programming flow for MAX+PLUS II software.

Figure 1. MAX+PLUS II Device Programming Flow

Altera-provided items are shown in blue.

You can program devices with Altera programming hardware and MAX+PLUS II Programmer software installed on a 486- or Pentium-based PC or a UNIX workstation, or with programming hardware and software available from other manufacturers. Table 1 shows the available Altera programming hardware options on PCs and UNIX workstations.

Table 1. Altera Programming Hardware
Programming Hardware Option	PCs	UNIX Work- stations	MAX® 3000A Devices	Classic® & MAX 5000 Devices	MAX 7000 & MAX 7000E Devices	MAX 7000A, MAX 7000AE, MAX 7000B, MAX 7000S MAX 9000 & MAX 9000A Devices	FLEX® 6000, FLEX 6000A, FLEX 8000, FLEX 10K, FLEX 10KA, FLEX 10KB, & FLEX 10KE Devices	In-System Programming/ Configuration
Logic Programmer card, PL-MPU Master Programming Unit, and device-specific adapters
BitBlaster™ Download Cable
ByteBlasterMV™ Download Cable
MasterBlaster™ Download Cable

If you wish to transfer programming files from a UNIX workstation to a PC over a network with File Transfer Protocol (FTP) or other similar transfer programs, be sure to select binary transfer mode.

Programming hardware from other manufacturers varies, but typically consists of a device connected to one of the serial ports on the workstation. Various vendors, such as Data I/O and BP Microsystems, supply hardware and software for programming Altera devices.

Related Topics:

Go to Compiling Projects with MAX+PLUS II Software for information on creating programming files.

	Go to the following topics, which are available on the web, for additional information:
	MAX+PLUS II Development Software Altera Programming Hardware FLEX Devices MAX Devices Classic Device Family

Last updated on December 6, 1999 for the MAX+PLUS II software version 9.4.

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