Creating Composer Schematics for Use with MAX+PLUS II Software
You can create Composer schematics and convert them into EDIF Input Files (.edf) that can be processed with the MAX+PLUS® II Compiler. To create a Composer schematic for use with the MAX+PLUS II software, follow these steps:
- Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment.
- Start the Composer schematic editor from the <working directory> by typing
icds  at a UNIX prompt. Use the graphical user interface to structure and organize your files to create an environment that facilitates entering and processing designs. Go to Composer Project File Directory Structure for more information on directories in Composer.
- Choose Library Path Editor (Tools menu) to create the <design name> library. In the Library dialog box, type <project directory name> as the Library name and
./source/<design name> as the Path name. Choose Save (File menu), then choose Exit (File menu) to save the path.
- Choose Library Manager (Tools menu) to start Composer and create a new design.
- Type <project directory name> as the Library name, <design name> as the Cell name, and
schematic as the View name in the Library Manager dialog box and press the key.
- Enter primitives, megafunctions, and macrofunctions from the following libraries:
- MAX+PLUS II-compatible primitives, megafunctions, and macrofunctions are available in the Altera-provided alt_max2 component library.
- Input, output, and bidirectional pins are available in the Cadence basic library located under /cadence/etc/cdslib.
- MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.
- Enter meaningful instance names for all symbols and functions so that you can easily trace internal node names during simulation and debugging operations. For example, if an
a161 macrofunction is instantiated several times in one design, you should define a unique name for each instance. The instance name for each symbol is controlled by INST property. For more information on assigning properties, refer to the Cadence Composer User Guide.
- (Optional) To enter resource assignments in your Composer schematic, go to Entering Resource Assignments. You can also enter resource assignments from within the MAX+PLUS II software.
- (Optional) Functionally simulate the design with the Verilog-XL simulator. Altera provides Verilog HDL simulation modules in the /usr/maxplus2/simlib/composer/alt_max2/verilog and /usr/maxplus2/simlib/composer/alt_max2/verilogUdps directories. Go to Performing a Functional Simulation of a Composer Schematic with Verilog-XL Software for more information.
- Use the altout utility to generate an EDIF netlist file that can be imported into the MAX+PLUS II software, as described in Converting Composer Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the altout Utility.
- Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.
Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample Composer schematic files:
- /usr/maxplus2/examples/cadence/example2/fulladd
- /usr/maxplus2/examples/cadence/example5/fulladd2
- /usr/maxplus2/examples/cadence/example7/fa2
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Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
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