Instantiating the clklock Megafunction in Concept Schematics
You can instantiate the clklock phase-locked loop megafunction, which is supported in selected FLEX® 10K devices, in a Concept schematic. that employ a phase-locked loop (PLL).
To instantiate the clklock megafunction in Cadence Concept schematics, follow these steps:
- Choose the Add Part button from the toolbar or type
add  in the Concept window to open the Component Browser window.
- Enter the
clklock megafunction:
- Choose alt_max2 (Library menu) and select clklock from the list box.
- Type
attribute, then select the clklock component. Change the CLOCKBOOST and INPUT_FREQUENCY values as needed. For detailed information on the clklock megafunction, choose Megafunctions/LPM from the MAX+PLUS® II Help menu.
- Choose Done.
- Continue with the steps necessary to complete your Concept schematic, as described in Creating Concept Schematics for Use with MAX+PLUS II Software.
Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample Concept schematic file, which includes clklock instantiation:
Related Links:
Feedback
Did this information help you?
If no, please log onto mySupport to file a technical request or enhancement.
Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
|
文档资料
> 
