Creating Hierarchical Projects in Concept Schematics
If you wish to create a hierarchical design that contains symbols representing other MAX+PLUS II-supported design files, such as
Altera® Hardware Description Language (AHDL) Text Design Files (.tdf), you can create a hollow-body symbol that represents a design file and then instantiate it in your Concept schematic. To create a hierarchical project in your Concept schematic, go through the following steps:
- Be sure to set up your working environment correctly, as described in Setting Up the
MAX+PLUS® II/Cadence Working Environment.
- Create a Concept schematic and save it in your working directory, as described in Creating Concept Schematics for Use with MAX+PLUS II Software.
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You can instantiate MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support. |
- Create the hollow-body symbol <design name> in Concept by typing the following command from the <working directory>/source directory that contains the lower-level design file <design name>.<extension>:
concept <design name>.body 
- Create a part file to indicate that the body is hollow:
- Add the
DEFINE and DRAWING bodies to the part drawing. These bodies should be the only two bodies in the drawing.
- Add the
TITLE=<design name> and the ABBREV=<design name> properties to the DRAWING body to identify the drawing.
- Save the part drawing with the name <design name>.part.1.1.
- Regardless of the hardware description language (HDL) or schematic editor used to create the design, you must create a dummy Verilog HDL module to indicate to the concept2alt utility that the design is a "black box" that must pass untouched through the EDIF netlist file.
- Type
genview verilog in the Concept window.
- Type
logic when prompted for the Verilog View name.
- If you are using VerilogLink, you must type
genview verilog again, then type verilog_lib when prompted for the Verilog View name.
- Type
cd <design name>/logic at the UNIX prompt from the /source directory to change to the /source/<design name>/logic directory.
- Edit the verilog.v file to add the
cds_action = "ignore" parameter setting after the Input Declarations and Output Declarations sections. This parameter setting specifies that the <design name> should be treated as a "black box."
- To enter the symbol in the higher-level Concept schematic, choose the Add Part button, choose the name of the working SCALD directory, then choose the <design name> symbol from the Symbol menu.
- The MAX+PLUS II software uses the cadence.lmf Library Mapping File to map Concept symbols to equivalent MAX+PLUS II logic functions. To use custom symbols, you must create a custom LMF that maps your custom symbols to the equivalent EDIF Input File, Text Design File (TDF), or other design file. You will also need to specify this custom LMF in the EDIF Netlist Reader Settings dialog box before compiling with the MAX+PLUS II software. See Compiling Projects with MAX+PLUS II Software for more information.
- Continue with the steps necessary to complete your Concept schematic, as described in Creating Concept Schematics for Use with MAX+PLUS II Software.
Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample hierarchical AHDL and Concept schematic file:
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Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
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