文档资料 许可 在线购买 下载 全部页面 技术资料 产品型号

主页   |   产品   |   支持   |   最终市场   |   技术中心   |   教育与活动   |   公司介绍   |   在线购买

mySupport   |   器件   |   软件   |   IP   |   设计范例   |   参考设计

---

Modifying the Assignment & Configuration File with the setacf Utility

Altera provides the setacf utility to help you modify a project's Assignment & Configuration File (.acf) from the command line, without opening the file with a text editor. Type setacf -h at a UNIX or DOS prompt to get help on this utility.

---

Creating Verilog HDL Designs for Use with MAX+PLUS II Software

You can create Verilog HDL design files with the MAX+PLUS^® II Text Editor or another standard text editor and save them in the appropriate directory for you project. The MAX+PLUS II Text Editor offers the following advantages:

• Verilog HDL templates are available with the Verilog Templates command (Templates menu). These templates are also available in the ASCII verilog.tmp file, which is located in the /usr/maxplus2 directory.

• If you use the MAX+PLUS II Text Editor to create your Verilog HDL design, you can use the Syntax Coloring command (Options menu). The Syntax Coloring feature displays keywords and other elements of text in text files in different colors to distinguish them from other forms of syntax.

To create a Verilog HDL design that can be synthesized and optimized with Synergy software, go through the following steps:

1. You can instantiate the following MAX+PLUS II-provided logic functions in your Verilog HDL design:

   • The alt_max2 library, which contains the a_8count, a_8mcomp, a_8fadd, and a_81mux macrofunctions that are optimized for different Altera device families.

   • The clklock megafunction which enables phase-locked loop, or ClockLock^™, circuitry available on selected Altera FLEX^® 10K devices. Go to Instantiating the clklock Megafunction in VHDL or Verilog HDL for information.

   • T

产品    Quartus II       SOPC Builder       MAX+PLUS II       ModelSim-Altera     资源中心       简介       安装&许可       脚本        电路板设计& I/O       网表阅读器 & 综合       编译增强特性       优化       功耗管理    TimeQuest时序分析器       标准时序分析器       仿真 & 确认       片内调试       HardCopy设计     软件资源       操作系统支持       驱动安装     下载与许可       下载    许可     Quartus II EDA 支持       Quartus II 接口    综合工具    仿真工具    验证工具    时序分析工具    再综合工具    电路板级工具     老版软件EDA支持       供应商类       工具类       功能类	Modifying the Assignment & Configuration File with the setacf Utility Altera provides the setacf utility to help you modify a project's Assignment & Configuration File (.acf) from the command line, without opening the file with a text editor. Type setacf -h at a UNIX or DOS prompt to get help on this utility. Performing a Functional Simulation of a Composer Schematic with Verilog-XL Software You can perform a functional simulation of a Cadence Composer schematic with the Verilog-XL simulator before compiling your project with the MAX+PLUS® II software. To functionally simulate a Composer schematic, follow these steps: Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment. Create a Composer schematic and save it in your working directory, as described in Creating Composer Schematics for Use with MAX+PLUS II Software. In Composer, select Simulation from the Tools drop-down list. Select Verilog-XL to start the Verilog-XL Integration Control window. When you are ready to compile the project, generate an EDIF netlist file <design name>.edf with the altout utility, as described in Converting Composer Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the altout Utility. Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software. Creating Hierarchical Projects in Composer Schematics If you wish to create a hierarchical design that contains symbols representing other design files, such as Altera® Hardware Description Language (AHDL) Text Design Files (.tdf), you can create a hollow-body symbol that represents a design file and then instantiate it in your Composer schematic. To create a hierarchical project in your Composer schematic, follow these steps: Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS® II/Cadence Working Environment. Create a Composer schematic and save it in your working directory, as described in Creating Composer Schematics for Use with MAX+PLUS II Software. 主页 > 支持 > 软件 > Using Cadence Tools with MAX+PLUS II Software 打印此页 发送此页 Go to "Devices & Adapters" and "Assigning a Device" in MAX+PLUS II Help for information on device pin-outs and assigning devices, respectively, in the MAX+PLUS II software. Go to Back-Annotating MAX+PLUS II Pin Assignments to Design Architect Symbols for information on back-annotating pin assignments in Mentor Graphics Design Architect schematics. Assigning Cliques You can define a group of logic functions as a single, named unit, called a clique. The MAX+PLUS® II Compiler attempts to place all logic in the clique in the same logic array block (LAB) to ensure optimum speed. If the project does not use multi-LAB devices, or if it is not possible to fit all clique members into a single LAB, the clique assignment ensures that all members of a clique are placed in the same device. In FLEX® 6000, FLEX 8000, FLEX 10K, and MAX® 9000 devices the Compiler also attempts to place the logic in LABs in the same row. Cliques therefore allow you to partition a project so that only a minimum number of signals travel between LABs, and to ensure that no unnecessary LAB-to-LAB or device-to-device delays exist on critical timing paths. Using Cadence Tools with MAX+PLUS II Software The following topics describe how to use a variety of Cadence tools as part of a complete design flow that includes the MAX+PLUS® II software. If you use only one Cadence tool, click List by Tool and select the tool name to view the list of topics only for that tool. Click on one of the following topics for information: This file is suitable for printing only. It does not contain hypertext links that allow you to jump from topic to topic. Setting Up the MAX+PLUS II/Cadence Working Environment Software Requirements Setting Up the MAX+PLUS II/Cadence Concept Work Environment for a Sun SPARCstation Running SunOS Software MAX+PLUS II/Cadence Interface File Organization MAX+PLUS II Directory Structure Concept & RapidSIM Local Work Area Directory Structure Concept & HDL Direct Project Directory Structure Composer Project File Directory Structure Altera-Provided Logic & Symbol Libraries Compiling the VITAL Library for Use with Leapfrog Software Compiling the alt_mf Library Design Flow for All Cadence Tools Design Entry Design Entry Flow Concept Creating Concept Schematics for Use with MAX+PLUS II Software Instantiating the clklock Megafunction in Concept Schematics Instantiating LPM & Other Parameterized Functions in Concept Schematics Entering Resource Assignments Assigning Pins, Logic Cells & Chips Assigning Cliques Assigning Logic Options Modifying the Assignment & Configuration File with the setacf Utility Performing a Functional Simulation of a Concept Schematic with the hdlconfig Utility & Verilog-XL Software Performing a Functional Simulation of a Concept Schematic with VerilogLink & Verilog-XL Software Creating Hierarchical Projects in Concept Schematics Converting Concept Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the concept2alt Utility Composer Creating Composer Schematics for Use with MAX+PLUS II Software Entering Resource Assignments Assigning Pins, Logic Cells & Chips Assigning Cliques Assigning Logic Options Modifying the Assignment & Configuration File with the setacf Utility Performing a Functional Simulation of a Composer Schematic with Verilog-XL Software Creating Hierarchical Projects in Composer Schematics Converting Composer Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the altout Utility VHDL Creating VHDL Designs for Use with MAX+PLUS II Software Instantiating the clklock Megafunction in VHDL or Verilog HDL Entering Resource Assignments Modifying the Assignment & Configuration File with the setacf Utility Verilog HDL Creating Verilog HDL Designs for Use with MAX+PLUS II Software Instantiating the clklock Megafunction in VHDL or Verilog HDL Entering Resource Assignments Modifying the Assignment & Configuration File with the setacf Utility Synthesis & Optimization VHDL Synthesizing & Optimizing VHDL Files with Synergy Software Converting VHDL Designs into MAX+PLUS II-Compatible EDIF Netlist Files with the vlog2alt or altout Utility Verilog HDL Synthesizing & Optimizing Verilog HDL Files with Synergy Software Converting Verilog HDL Designs into MAX+PLUS II-Compatible EDIF Netlist Files with the vlog2alt Utility Compilation Project Compilation Flow Compiling Projects with MAX+PLUS II Software Simulation Project Simulation Flow Initializing Registers in VHDL & Verilog Output Files for Power-Up before Simulation Performing a Timing Simulation with RapidSIM Software Performing a Timing Simulation with Verilog-XL Software Performing a Timing Simulation with Leapfrog Software Compiling the VITAL Library for Use with Leapfrog Software Compiling the alt_mf Library Device Programming Programming Altera Devices Related Topics: MAX+PLUS II Development Software Altera Programming Hardware Cadence web site (http://www.cadence.com) Setting Up the MAX+PLUS II/Cadence Working Environment To use MAX+PLUS® II software with Cadence software, you must first install the MAX+PLUS II software, then establish an environment that facilitates entering and processing designs. The MAX+PLUS II/Cadence interface is installed automatically when you install the MAX+PLUS II software on your computer. Go to MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual for more information on installation and details on the directories that are created during MAX+PLUS II installation. Go to MAX+PLUS II/Cadence Interface File Organization for information about the MAX+PLUS II/Cadence directories that are created during MAX+PLUS II installation. The information presented here assumes that you are using the C shell and that your MAX+PLUS II system directory is /usr/maxplus2. If not, you must use the appropriate syntax and procedures to set environment variables for your shell. To set up your working environment for the MAX+PLUS II/Cadence interface, follow these steps: Ensure that you have correctly installed the MAX+PLUS II and Cadence software versions described in the MAX+PLUS II/Cadence Software Requirements. Add the following environment variables to your .cshrc file: setenv ALT_HOME /usr/maxplus2 setenv CDS_INST_DIR <Cadence system directory path> Add the $ALT_HOME/cadence/bin and $CDS_INST_DIR/tools/bin directories to the PATH environment variable in your .cshrc file. Make sure these paths are placed before the Cadence hierarchy path. Add /usr/dt/lib and /usr/ucb/lib to the LD_LIBRARY_PATH environment variable in your .cshrc file. Create a new cds.lib file in your working directory or edit an existing one so that it includes all of the following lines that apply to the Cadence tools you have installed: DEFINE alt_syn ${ALT_HOME}/simlib/concept/alt_syn DEFINE lpm_syn ${ALT_HOME}/simlib/concept/lpm_syn DEFINE alt_lpm ${ALT_HOME}/simlib/concept/alt_lpm DEFINE alt_mf ${ALT_HOME}/simlib/concept/alt_mf DEFINE alt_max2 ${ALT_HOME}/simlib/concept/alt_max2 DEFINE alt_max2 ${ALT_HOME}/simlib/composer/alt_max2/alt_max2 DEFINE alt_vtl $ALT_HOME/simlib/concept/alt_vtl/lib DEFINE altera $ALT_HOME/simlib/concept/alt_mf/lib SOFTINCLUDE $CDS_INST_DIR/tools/leapfrog/files/cds.lib DEFINE <design name>. Copy the /usr/maxplus2/maxplus2.ini file to your $HOME directory: cp /usr/maxplus2/maxplus2.ini $HOME chmod u+w $HOME/maxplus2.ini The maxplus2.ini file contains both Altera- and user-specified initialization parameters that control the MAX+PLUS II software, such as MAX+PLUS II symbol and logic function library paths and the current project name. The MAX+PLUS II installation procedure creates and copies the maxplus2.ini file to the /usr/maxplus2 directory. Normally, you do not have to edit your local copy of maxplus2.ini because the MAX+PLUS II software updates the file automatically whenever you change any parameters or settings. However, if you move the max2lib and max2inc library subdirectories, you must update the file. Go to "Creating & Using a Local Copy of the maxplus2.ini File" in MAX+PLUS II Help for more information. If you are using Concept on a Sun SPARCstation running SunOS, go to Setting Up the MAX+PLUS II/Cadence Concept Work Environment for a Sun SPARCstation Running SunOS Software to install the redifnet EDIF netlist reader utility. If you are using Synergy software, edit the hdl.var file located in your working directory to include the following line: DEFINE work <design name> Set up an appropriate directory structure for the tool(s) you are using. See the following topics for information: Composer Project File Directory Structure Concept & RapidSIM Local Work Area Directory Structure Related Topics: Go to the following topics, which are available on the web, for additional information: MAX+PLUS II Getting Started version 8.1 (5.4 MB) This manual is also available in 4 parts: Preface & Section 1: MAX+PLUS II Installation Section 2: MAX+PLUS II - A Perspective Section 3: MAX+PLUS II Tutorial Appendices, Glossary & Index MAX+PLUS II/Cadence Software Requirements The following table shows the software applications that are used to generate, process, synthesize, and verify a project with MAX+PLUS® II and Cadence software: Cadence Altera version 97A: Concept Composer ValidCOMPILER concept2alt vlog2alt altout VerilogLink Synergy HDL Direct (Concept 2.0 or later) Non-Graphic Simulation Environment (SE) RapidSIM, Verilog-XL, or Leapfrog redifnet (SunOS only) MAX+PLUS II version 9.4 The MAX+PLUS II read.me file provides up-to-date information on which versions of Cadence software applications are supported by the current version of MAX+PLUS II. It also provides information on installation and operating requirements. You should read the read.me file on the CD-ROM before installing the MAX+PLUS II software. After installation, you can open the read.me file from the MAX+PLUS II Help menu. Setting Up the MAX+PLUS II/Cadence Concept Work Environment for a Sun SPARCstation Running SunOS Software If you are using Concept software on a Sun SPARCstation running SunOS software, you should also install the redifnet EDIF netlist reader utility to convert Concept schematics into MAX+PLUS II-compatible EDIF netlist files. To install the redifnet utility, follow these steps: Copy the redifnet directory from the /usr/maxplus2/simlib/concept/edifnet directory to the Cadence system directory. Copy the redifnet and pinmap_start files from the /usr/maxplus2/simlib/concept/edifnet/bin directory to the /<Cadence system directory path>/tools/bin. Specify the -/usr/maxplus2/simlib/concept/edifnet/max2sim map file as a PIN_MAP_FILE in the redifnet.cmd file. (Optional) Modify existing templates for directive files such as compiler.cmd, vloglink.cmd, and global.cmd. These templates are located in the /usr/maxplus2/simlib/concept/edifnet/templates directory. (Optional) Modify the expansion.dat and max2sim.map files in the /usr/maxplus2/simlib/concept/edifnet directory. MAX+PLUS II/Cadence Interface File Organization Table 1 shows the MAX+PLUS® II/Cadence interface subdirectories that are created in the MAX+PLUS II system directory (by default, the /usr/maxplus2 directory) during MAX+PLUS II installation. For information on the other directories that are created during MAX+PLUS II installation, see "MAX+PLUS II File Organization" in MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual. Table 1. MAX+PLUS II Directory Organization Directory Description ./lmf Contains the Altera-provided Library Mapping File, cadence.lmf, that maps Cadence logic functions to equivalent MAX+PLUS II logic functions. ./examples/cadence Contains the sample files for Cadence software discussed in these ACCESSSM Key Guidelines. ./cadence Contains the AMPLE userware for the MAX+PLUS II/Cadence interface. ./simlib/concept/alt_max2 Contains the MAX+PLUS II primitives, including CARRY, CASCADE, EXP, GLOBAL, LCELL, SOFT, OPNDRN, DFFE (D flipflop with Clock Enable), and DFFE6K (D flipflop with Clock Enable and both Clear and Preset for FLEX® 6000 devices only) for use with Concept software. ./simlib/composer/alt_max2 Contains the MAX+PLUS II primitives, including CARRY, CASCADE, EXP, GLOBAL, LCELL, SOFT, OPNDRN, DFFE (D flipflop with Clock Enable), and DFFE6K (D flipflop with Clock Enable and both Clear and Preset for FLEX 6000 devices only) for use with Composer software. ./simlib/concept/alt_lpm Contains the MAX+PLUS II megafunctions, including library of parameterized modules (LPM) functions, for use with Concept software. ./simlib/concept/max2sim Contains the MAX+PLUS II/Concept simulation model library, max2_sim, for use with RapidSIM software. ./simlib/concept/alt_syn Contains the MAX+PLUS II synthesis library, alt_syn, for use with Synergy and Concept software, and the vlog2alt utility. ./simlib/composer/alt_syn Contains the MAX+PLUS II synthesis library, alt_syn, for use with Synergy and Composer software. ./simlib/concept/lpm_syn Contains the Cadence LPM library, lpm_syn, for use with Synergy and Concept software. ./simlib/composer/lpm_syn Contains the Cadence LPM library, lpm_syn, for use with Synergy and Composer software. ./simlib/concept/alt_mf Contains the MAX+PLUS II VHDL logic function library. (a_8count is for the MAX® 7000 and MAX 9000 device families only.) ./simlib/concept/edifnet/templates Contains template files for Concept directives, i.e., global.cmd, compiler.cmd, vloglink.cmd, verilog.cmd, and master.local. ./simlib/concept/alt_max2/verilogUdps Contains Verilog HDL modules that are the equivalent of the primitives contained in alt_max2 library for use with Concept software. ./simlib/composer/alt_max2/verilogUdps Contains Verilog HDL modules that are the equivalent of the primitives contained in alt_max2 library for use with Composer software. ./simlib/concept/alt_vtl ./simlib/composer/alt_vtl Contains VITAL library source files for use with Concept or Composer software. ./simlib/composer/alt_max2/verilog Contains simulation modules for all symbols in the alt_max2 Composer library. Related Topics: Go to the following topics, which are available on the web, for additional information: MAX+PLUS II Getting Started version 8.1 (5.4 MB) This manual is also available in 4 parts: Preface & Section 1: MAX+PLUS II Installation Section 2: MAX+PLUS II - A Perspective Section 3: MAX+PLUS II Tutorial Appendices, Glossary & Index FLEX Devices MAX Devices Classic Device Family MAX+PLUS II Directory Structure In the MAX+PLUS® II software, a project name is the name of a top-level design file, without the filename extension. This design file can be an EDIF, Verilog HDL, or VHDL netlist file; an AHDL Text Design File (TDF); or any other MAX+PLUS II-supported design file. The EDIF netlist file must be created by the altout or concept2alt utility and imported into the MAX+PLUS II software as an EDIF Input File (.edf). Project design files and output files are stored in the project directory, with the exception of standard library functions provided by Altera or another EDA tool vendor. The MAX+PLUS II software stores the connectivity data on the links between design files in a hierarchical project in a Hierarchy Interconnect File (.hif), but refers to the entire project only by its project name. The MAX+PLUS II Compiler uses the HIF to build a single, fully flattened project database that integrates all design files in a project hierarchy. Concept & RapidSIM Local Work Area Directory Structure When the redifnet utility imports an EDIF netlist file for the RapidSIM software, it creates a SCALD directory for your project. However, creating this directory may overwrite the directory that was created for the original Concept schematic. To prevent overwriting this directory, you should create a file structure that helps you manage your design files. Altera recommends that you create the following three directories for your design files. Directory: Description:   ./source Create Concept schematics and generate EDIF netlist files with the wedifnet utility in the source directory. ./max2 Copy the EDIF Input File (.edf) from the source directory to this directory to compile the file with the MAX+PLUS® II software. ./dest Copy the EDIF Output File (.edo) from the max2 directory to this directory to run the redifnet and RapidSIM software. Copies of the appropriate directives files for Cadence tools must be present in both the source and dest directories. Figure 1 shows Altera's recommended file structure. Figure 1. Recommended File Structure Concept & HDL Direct Project Directory Structure Concept software generates the following files for each schematic: <drawing name>/logic.1.1 <drawing name>/logic_bn.1.1 <drawing name>/logic_cn.1.1 <drawing name>/logic_dp.1.1 For designs that use HDL Direct software, Concept software also generates the following files: <drawing name>/logic_dp.1.1 <drawing name>/logic_vd.1.1 <drawing name>/logic/verilog.v <drawing name>/logic/vhdl.vhd <drawing name>/logic/hdldirect.dat <drawing name>/entity/vhdl.vhd These files are stored in their own <drawing name> directories. However, hierarchical relationships between files are not reflected in the file directory structure. The local SCALD directory has an entry for all <drawing name> directories. Cadence software automatically manages drawing storage and retrieval operations through this special directory. The SCALD directory should have the same name as the UNIX project directory, but with the extension .wrk. Figure 1 shows a sample file structure, with project1 as the UNIX project directory, and project1.wrk as the SCALD directory. When the concept2alt utility converts the schematic into an EDIF netlist file, it processes the design information and all related file subdirectories, then creates the EDIF netlist file in the directory defined by the user. The EDIF netlist file is named <project name>.edf, where <project name> is the name of the top-level design file. Figure 1 shows the Cadence project file structure. Figure 1. Cadence Project File Structure Composer Project File Directory Structure The Composer software generates the following files for each schematic (where x represents a Composer-generated number): <drawing name>_x/schema_59.0_x <drawing name>_x/schema_59.0_x% Altera-Provided Logic & Symbol Libraries The MAX+PLUS® II/Cadence environment provides four logic and symbol libraries that are used for compiling, synthesizing, and simulating designs. You can create your own libraries of custom symbols and logic functions in Concept and Composer. You can use custom symbols to incorporate an EDIF Input File, Text Design File (TDF), or any other MAX+PLUS II-supported design file into a project. MAX+PLUS II uses the cadence.lmf Library Mapping File to map standard Concept or Composer symbols to equivalent MAX+PLUS II logic functions. To use custom symbols, you can create a custom LMF that maps your custom symbols to the equivalent MAX+PLUS II-supported design file. You must also specify the directory that contains the MAX+PLUS II-supported design file(s) as a user library with the MAX+PLUS II User Libraries command (Options menu). Go to "Library Mapping File" and "Cadence Library Mapping File (cadence.lmf)" in MAX+PLUS II Help for more information. The alt_max2 Library You can enter a Concept or Composer Design Architect schematic with primitives and macrofunctions from the Altera-provided symbol library alt_max2. The alt_max2 library includes 74-series macrofunctions and several MAX+PLUS II primitives with corresponding Verilog HDL simulation models for controlling design synthesis and fitting. It also includes four macrofunctions--a_8count, a_8mcomp, a_8fadd, and a_81mux--that are optimized for different device families, and the clklock phase-locked loop megafunction, which is supported by some FLEX® 10K devices, with corresponding Verilog HDL and VHDL simulation models. See Table 1. Choose Old-Style Macrofunctions and/or Primitives from the MAX+PLUS II Help menu for more information on functions in the alt_max2 library. The alt_lpm Library The Altera-provided alt_lpm library, which is available for Concept and Verilog HDL designs, includes standard functions from the library of parameterized modules (LPM) 2.1.0, except the truth table, finite state machine, and pad functions. Other parameterized functions, including cycle-shared FIFO (csfifo) and cycle-shared dual-port RAM (csdpram) are also included. The LPM standard defines a set of parameterized modules (i.e., parameterized megafunctions) and their corresponding representations in an EDIF netlist file. These logic functions allow you to create and functionally simulate an LPM-based design without targeting a specific device family. The parameters you specify for each LPM function determine the simulation models that will be generated. After the design is completed, you can target the design to any device family. In designs created with Concept, the Altera alt_lpm library works only with HDL Direct and the hdlconfig utility. Choose Megafunctions/LPM from the MAX+PLUS II Help menu for more information about LPM functions in the alt_lpm library. The lpm_syn Library The lpm_syn library contains the Altera-provided parameterized functions. The lpm_syn library is similar to the alt_lpm library, except that it contains VHDL and Verilog HDL logic functions for use with Synergy, Concept, and Composer software. The alt_mf Library Altera provides a VHDL logic function library, alt_mf, that currently includes four macrofunctions--a_8count, a_8mcomp, a_8fadd, and a_81mux--for controlling design synthesis and fitting. These elements can be instantiated directly in your VHDL file. To designate that these logic functions should pass untouched through the EDIF netlist file to the MAX+PLUS II Compiler, you must select the Maintain attribute constraint for instances of these functions before running the Synergy software. These models allow you to perform functional VHDL simulation while maintaining an architecture-independent VHDL description. Table 1 shows the MAX+PLUS II-specific logic functions. Table 1. MAX+PLUS II-Specific Logic Functions Macrofunctions Note (1) Primitives Name Description Name Description Name Description 8fadd 8-bit full adder LCELL Logic cell buffer EXP MAX® 5000, MAX 7000, and MAX 9000 Expander buffer 8mcomp 8-bit magnitude comparator GLOBAL Global input buffer SOFT Soft buffer 8count Note (2) 8-bit up/down counter CASCADE FLEX 6000, FLEX 8000, and FLEX 10K cascade buffer OPNDRN Open-drain buffer 81mux 8-to-1 multiplexer CARRY FLEX 6000, FLEX 8000, and FLEX 10K carry buffer DFFE DFFE6K Note (3) D-type flipflop with Clock Enable clklock Phase-locked loop Notes: Logic function names that begin with a number must be preceded by "a_" in VHDL designs. For example, 8fadd must be specified as a_8fadd. The a_8count logic function is for the MAX 7000 and MAX 9000 device families only. For designs that are targeted to FLEX 6000 devices, you should use the DFFE primitive only if the design contains either a Clear or Preset signal, but not both. If your design contains both a Clear and a Preset signal, you must use the DFFE6K primitive. Related Topics: Go to the following topics, which are available on the web, for additional information: FLEX Devices MAX Devices Classic Device Family Compiling the VITAL Library for Use with Leapfrog Software If you wish to use MAX+PLUS® II-generated Standard Delay Format (SDF) Output Files (.sdo) that contain timing information when performing post-compilation timing simulation with Leapfrog software, you must first compile the VITAL library source files. The VITAL Timing and Primitive package files are located in the $CDS_INST_DIR/tools/leapfrog/files/IEEE.src directory. To compile the alt_vtl library, follow these steps: Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment. For example, you must ensure that the appropriate directories are specified in the cds.lib file that is located in your working directory. Create a VHDL design, as described in Creating VHDL Designs for Use with MAX+PLUS II Software and save it in your working directory. Change to the alt_vtl directory by typing cd /usr/maxplus2/simlib/concept/alt_vtl at the UNIX prompt. Edit the hdl.var file located in your working directory to include the following line: DEFINE WORK alt_vtl Create the /usr/maxplus2/simlib/concept/alt_vtl/lib directory. Type the following commands at the UNIX prompt from the /usr/maxplus2/simlib/concept/alt_vtl directory to compile the library: cv -message -file alt_vtl.vhd cv -message -file alt_vtl.cmp Compiling the alt_mf Library If your VHDL design uses functions from the alt_mf library, you must compile this library. To compile the alt_mf library, follow these steps: Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS® II/Cadence Working Environment. For example, you must ensure that the appropriate directories are specified in the cds.lib file located in your working directory. Change to the alt_mf directory by typing cd /usr/maxplus2/simlib/concept/alt_mf at the UNIX prompt. Edit the hdl.var file located in your working directory to include the following line: DEFINE work alt_mf Type the following commands at the UNIX prompt from the /usr/maxplus2/simlib/concept/alt_mf directory to compile the library: cv -message -file ./src/mf.vhd cv -message -file ./src/mf_components.vhd Design Flow for All Cadence Tools Figure 1 shows the typical design flow for logic circuits created and processed with Cadence and MAX+PLUS® II software. Design Entry Flow, Project Compilation Flow, Project Simulation Flow, and Device Programming Flow show detailed diagrams of each stage of the design flow. Figure 1. Design Flow between Cadence & MAX+PLUS II Software Cadence Design Entry Flow Figure 1 shows the design entry flow for the MAX+PLUS® II/Cadence interface. Figure 1. MAX+PLUS II/Cadence Design Entry Flow Altera-provided items are shown in blue. Creating Concept Schematics for Use with MAX+PLUS II Software You can create Concept schematics and convert them to EDIF Input Files (.edf) that can be processed with the MAX+PLUS® II Compiler. To create a Concept schematic for use with the MAX+PLUS II software, go through the following steps: Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment. Make sure the required directive files are in the /<working directory>/<design name>/source directory. If not, you can use the Altera-provided template files located in the following directories: /usr/maxplus2/simlib/concept/edifnet/templates /usr/maxplus2/simlib/concept/edifnet/redifnet Start the Concept schematic editor by typing concept <design name> at a UNIX prompt from the /<working directory>/source directory. Use the graphical user interface to structure and organize your files to create an environment that facilitates entering and processing designs. Go to Concept & RapidSIM Local Work Area Directory Structure for more information on directories in Concept. To write a Verilog HDL text file whenever the design is saved, choose the Block button in the Concept window. To use the HDL Direct utility to process your design, turn on the HDL Direct On option in the Concept window. Go to Concept & HDL Direct Project Directory Structure for information on the files generated by Concept software when using the HDL Direct utility. Enter primitives, megafunctions, and macrofunctions from the following Altera-provided component libraries: alt_max2 includes macrofunctions, megafunctions, and primitives. alt_lpm includes library of parameterized modules (LPM) functions (available only if you use HDL Direct software). See the following topics for instructions for specific functions: Instantiating LPM & Other Parameterized Functions in Concept Schematics Instantiating the clklock Megafunction in Concept Schematics You can instantiate MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support. If you wish to create a hierarchical design that contains symbols representing other design files, such as Altera® Hardware Description Language (AHDL) Text Design Files, go to Creating Hierarchical Projects in Concept Schematics. Enter meaningful instance names for all symbols and functions so that you can easily trace internal node names during simulation and debugging operations. For example, if an a161 macrofunction is instantiated several times in one design, you should define a unique name for each instance. The instance name for each symbol is controlled by INST property. For more information on assigning properties, refer to the Cadence Concept Schematic User Guide. Enter input, output, and bidirectional ports: If you turned on the HDL Direct On option in step 4, add inport and outport symbols from the hdl_direct_lib library to the interface symbols. If you are not using HDL Direct, use flag symbols from the standard library to indicate input, output, and bidirectional ports. Be sure to end pin names with ¥I to identify them as interface signals. If a pin is not used, leave it floating. The concept2alt utility removes all unconnected pins when it generates an EDIF netlist file. (Optional) To enter resource assignments in your Concept schematic, go to Entering Resource Assignments. You can also enter resource assignments from within the MAX+PLUS II software. (Optional) Perform a functional simulation, as described in one of the following topics: Performing a Functional Simulation of a Concept Schematic with the hdlconfig Utility & Verilog-XL Software Performing a Functional Simulation of a Concept Schematic with VerilogLink & Verilog-XL Software Use the concept2alt utility to generate an EDIF netlist file that can be imported into the MAX+PLUS II software, as described in Converting Concept Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the concept2alt utility. Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software. Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample Concept schematic files: /usr/maxplus2/examples/cadence/example1/fulladd /usr/maxplus2/examples/cadence/example4/fulladd2 /usr/maxplus2/examples/cadence/example6/fa2 /usr/maxplus2/examples/cadence/example12/fifo Instantiating the clklock Megafunction in Concept Schematics You can instantiate the clklock phase-locked loop megafunction, which is supported in selected FLEX® 10K devices, in a Concept schematic. that employ a phase-locked loop (PLL). To instantiate the clklock megafunction in Cadence Concept schematics, follow these steps: Choose the Add Part button from the toolbar or type add in the Concept window to open the Component Browser window. Enter the clklock megafunction: Choose alt_max2 (Library menu) and select clklock from the list box. Type attribute, then select the clklock component. Change the CLOCKBOOST and INPUT_FREQUENCY values as needed. For detailed information on the clklock megafunction, choose Megafunctions/LPM from the MAX+PLUS® II Help menu. Choose Done. Continue with the steps necessary to complete your Concept schematic, as described in Creating Concept Schematics for Use with MAX+PLUS II Software. Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample Concept schematic file, which includes clklock instantiation: /usr/maxplus2/examples/cadence/example12/fifo Related Topics: Go to FLEX 10K Device Family, which is available on the web, for additional information. > Instantiating LPM & Other Parameterized Functions in Concept Schematics You can use library of parameterized modules (LPM) functions and other Altera®-provided parameterized functions in Concept schematics if you also use the HDL Direct utility. To instantiate LPM functions, go through the following steps: Choose the Add Part button from the toolbar or type add from the Concept window to open the Component Browser window. Choose alt_lpm (Library menu). All functions in the alt_lpm library are MAX+PLUS® II-compatible. Choose Megafunctions/LPM from the MAX+PLUS II Help menu to get detailed information on all supported parameterized functions. Type attribute, then click on each component to set parameters for each function. See General Guidelines below for additional information. Add inport and outport symbols from the hdl_direct_lib library to the interface signals. Use the supply_0 and supply_1 symbols from the hdl_direct_lib library to connect a net to GND or VCC. Continue with the steps necessary to complete your Concept schematic, as described in Creating Concept Schematics for Use with MAX+PLUS II Software. Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample Concept schematic file, which includes LPM function instantiation: /usr/maxplus2/examples/cadence/example12/fifo General Guidelines If a pin is not used, leave it floating. The concept2alt utility removes all unconnected pins when it generates an EDIF netlist file. For the csfifo function, the value of the LPM_NUMWORDS parameter must be between 2LPM_WIDTHAD-1 and 2LPM_WIDTHAD. Make sure that any hexadecimal (Intel-format) file (.hex) that you use to specify the initial content of a memory does not have the same name as the design file name. Make sure that all properties and value strings are in uppercase letters, except the filename specified with the LPM_FILE property, which should use the actual case of the filename. Choose the Set button in the Concept window and choose CAPS_LOCK_OFF for the CAPS LOCK option. Only the LPM_POLARITY parameter (which can be set to INVERT or NORMAL) can determine the polarity of the bus or pin. You can display a bubble in the Concept schematic to indicate an inverted pin by typing BUBBLE in the Concept command window and selecting the appropriate pin. However, the bubble does not determine the polarity of the pin or bus. Avoid using the Replace button in the Concept window to replace old symbols with new ones: you may accidentally set unwanted properties. Instead, you should use the Delete button to delete old symbols and the Add button to add new symbol(s). Entering Resource Assignments The MAX+PLUS® II software allows you to enter a variety of resource and device assignments for your projects. Resource assignments are used to assign logic functions to a particular pin, logic cell, I/O cell, embedded cell, row, column, Logic Array Block (LAB), Embedded Array Block (EAB), chip, clique, local routing, logic option, timing requirement, or connected pin group. In MAX+PLUS II software, you can enter all types of resource and device assignments with Assign menu commands. You can also enter pin, logic cell, I/O cell, embedded cell, LAB, EAB, row, and column assignments in the MAX+PLUS II Floorplan Editor. The Assign menu commands and the Floorplan Editor all save assignment information in the ASCII Assignment & Configuration File (.acf) for the project. In addition, you can edit ACFs manually in any standard text editor or with the setacf utility. Concept & Composer Schematics In both Concept and Composer schematics, you can assign a limited subset of these resource assignments by assigning properties to symbols. These properties are incorporated into the EDIF netlist file(s). The MAX+PLUS II software automatically converts assignment information from the EDIF Input File into the ACF format. For information on making MAX+PLUS II-compatible resource assignments, go to the following topics: Assigning Pins, Logic Cells & Chips Assigning Cliques Assigning Logic Options Modifying the Assignment & Configuration File with the setacf Utility Go to the Cadence Concept Schematic User Guide and Composer Reference User Guide for details on how to assign properties. Go to "Resource Assignments in EDIF Input Files" and "Assigning Resources in a Third-Party Design Editor" in MAX+PLUS II Help for more information on assignments or properties that can be assigned in Concept and Composer. Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample Concept and Composer schematic files, which include resource assignments: /usr/maxplus2/examples/cadence/example6/fa2 (Concept) /usr/maxplus2/examples/cadence/example7/fa2 (Composer) VHDL & Verilog HDL Design Files For Verilog HDL- and VHDL-based designs, you must use the MAX+PLUS II software or the setacf utility to enter resource assignments. For information on using the setacf utility, go to Modifying the Assignment & Configuration File with the setacf Utility. Related Topics: For information on entering assignments in the MAX+PLUS II software with Assign menu commands or in an ACF, go to "resource assignments" or "ACF, format" in MAX+PLUS II Help using Search for Help on (Help menu). Assigning Pins, Logic Cells & Chips You can assign a single logic function to a specific pin or logic cell (including I/O cells and embedded cells) within a chip, and assign one or more functions to a specific chip. A chip is a group of logic functions defined as a single, named unit, which can be assigned to a specific device. You can assign a signal to a particular pin to ensure that the signal is always associated with that pin, regardless of future changes to the project. If you wish to set and maintain the performance of your project, assigning logic to a specific logic cell within a chip can minimize timing delays. In a project that is partitioned among multiple devices, you can assign logic functions that must be kept together in the same device to a chip. Chip assignments allow you to split a project so that only a minimum number of signals travel between devices, and to ensure that no unnecessary device-to-device delays exist on critical timing paths. You can assign a chip to a device in some EDA tools or in the MAX+PLUS® II software. Use the following syntax for chip, pin, and logic cell assignments: To assign a logic function to a chip: CHIP_PIN_LC=<chip name> For example: CHIP_PIN_LC=chip1 To assign a pin number within a chip: CHIP_PIN_LC=<chip name>@<pin number> For example: CHIP_PIN_LC=chip1@K2 To assign a logic cell, I/O cell, or embedded cell number: CHIP_PIN_LC=<chip name>@LC<logic cell number> CHIP_PIN_LC=<chip name>@IOC<I/O cell number> CHIP_PIN_LC=<chip name>@EC<embedded cell number> For example: CHIP_PIN_LC=chip1@LC44 Related Topics: Go to "Devices & Adapters" and "Assigning a Device" in MAX+PLUS II Help for information on device pin-outs and assigning devices, respectively, in the MAX+PLUS II software. Go to Back-Annotating MAX+PLUS II Pin Assignments to Design Architect Symbols for information on back-annotating pin assignments in Mentor Graphics Design Architect schematics. Assigning Cliques You can define a group of logic functions as a single, named unit, called a clique. The MAX+PLUS® II Compiler attempts to place all logic in the clique in the same logic array block (LAB) to ensure optimum speed. If the project does not use multi-LAB devices, or if it is not possible to fit all clique members into a single LAB, the clique assignment ensures that all members of a clique are placed in the same device. In FLEX® 6000, FLEX 8000, FLEX 10K, and MAX® 9000 devices the Compiler also attempts to place the logic in LABs in the same row. Cliques therefore allow you to partition a project so that only a minimum number of signals travel between LABs, and to ensure that no unnecessary LAB-to-LAB or device-to-device delays exist on critical timing paths. To assign a clique, use the following syntax: CLIQUE=<clique name> For example: CLIQUE=fast1 Related Topics: Assigning a Clique Guidelines for Achieving Maximum Speed Performance Assigning Logic Options Logic option and logic synthesis style assignments allow you to guide logic synthesis with logic optimization features that are specific to Altera® devices. You can assign logic options and styles to individual logic functions in your design. The MAX+PLUS® II Compiler also uses a device-family-specific default logic synthesis style for each project. Go to "Resource Assignments in EDIF Input Files" and "Assigning Resources in a Third-Party Design Editor" in MAX+PLUS II Help for complete and up-to-date information on logic option and logic synthesis style assignments, including definitions and syntax of these assignments. Modifying the Assignment & Configuration File with the setacf Utility Altera provides the setacf utility to help you modify a project's Assignment & Configuration File (.acf) from the command line, without opening the file with a text editor. Type setacf -h at a UNIX or DOS prompt to get help on this utility. Performing a Functional Simulation of a Concept Schematic with the hdlconfig Utility & Verilog-XL Software You can perform a functional simulation of a Concept schematic with the hdlconfig utility and Verilog-XL software before compiling your project with the MAX+PLUS® II software. To functionally simulate a Concept schematic, follow these steps: Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment. Create a Concept schematic and save it in your working directory, as described in Creating Concept Schematics for Use with MAX+PLUS II Software. Use the hdlconfig utility to create a Verilog HDL text file that contains the entire design. Type the following command at the UNIX prompt from the /<working directory>/<design name>/source directory: hdlconfig -a -c -r <design name> -o <design name>.v logic verilog_lib If your design contains RAM or ROM functions (e.g., lpm_ram_dq, lpm_ram_io, lpm_rom, scfifo, dcfifo, altdpram, and csdpram), run the vconfig utility to link the object convert_hex2ver.o to build a new Verilog-XL file that supports these functions by following these steps: Create a copy of the Verilog executable file by typing the following command at the UNIX prompt: cp -p $CDS_INST_DIR/tools/verilog/bin/verilog $CDS_INST_DIR/tools /verilog/bin/ verilog.bak.  Type vconfig at the UNIX prompt from the /usr/maxplus2/cadence/bin directory to start the script. Accept cr_vlog as the name of the output script. Accept 1 as the stand-alone target. Type new_verilog as the name for the Verilog-XL target. Respond Yes when you are prompted to compile for the Verilog-XL environment. Respond No when you are prompted to include the Dynamic LAI, STATIC LOGIC AUTOMATION, LMSI HARDWARE MODELER, Verilog Mixed-Signal, and CDC interfaces in this executable. Respond Yes when you are prompted to include the Standard Delay File Annotator (SDF). Specify /usr/maxplus2/verilog/veriuser.c when you are asked the name of the user template file. For more information about the contents of the veriuser.c file, you can refer to the veriuser.doc file, which is available in the Cadence Openbook product documentation. To locate this document, start Openbook, and choose Alphabetical List of Products from the main menu. Scroll through the pages until you locate the PLI 1.0 User Guide & Reference in the PLI section, and then continue to scroll through the document until you locate the veriuser.doc file under "Section A" and "PLI Code Examples." When you are asked the name of files to be linked with the Verilog-XL simulator, specify the hexadecimal (Intel-format) conversion file /usr/maxplus2/cadence/share/verilog/convert_hex2ver.o, followed by a single period (.). Run the output script cr_vlog to build the new Verilog-XL executable in the /usr/maxplus2/cadence/bin directory. Make sure that the $CDS_INST_DIR/tools/bin path appears at the beginning of the PATH statement in the .cshrc file. If your C language library installation is different from the default location /usr/lang/SC3.0.1, type the following command at the UNIX prompt: setenv C_DIR <C language library installation directory> If successful, replace the old Verilog executable file with the new one by typing the following command at the UNIX prompt: cp -p new_verilog $CDS_INST_DIR/tools/verilog/bin/verilog Generate the stimulus file for the design and start the Verilog-XL simulator by typing the following command at the UNIX prompt from the /<working directory>/<design name>/source directory: verilog -y /usr/maxplus2/simlib/concept/alt_max2/verilogUdps +libext+.v+.V <stimulus file name> <design name>.v When you are ready to compile the project, generate an EDIF netlist file <design name>.edf with the concept2alt utility, as described in Converting Concept Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the concept2alt Utility. Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software. Performing a Functional Simulation of a Concept Schematic with VerilogLink & Verilog-XL Software You can perform a functional simulation of a Concept schematic with VerilogLink and Verilog-XL software before compiling your project with the MAX+PLUS® II software. To functionally simulate a Concept schematic, follow these steps: Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment. Create a Concept schematic and save it in your working directory, as described in Creating Concept Schematics for Use with MAX+PLUS II Software. Generate the global.cmd, vloglink.cmd, verilog.cmd, and expansion.dat directive files. Type vloglink <design name> from the /<working directory>/source directory to create a vloglink.v file from the Concept schematic. Generate the stimulus file for the design and start the Verilog-XL simulator by typing the following command at the UNIX prompt from the /<working directory>/<design name>/source directory: verilog -y /usr/maxplus2/simlib/concept/alt_max2/verilogUdps +libext+.v+.V <stimulus file name> vloglink.v When you are ready to compile the project, generate an EDIF netlist file <design name>.edf with the concept2alt utility, as described in Converting Concept Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the concept2alt Utility . Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software. Creating Hierarchical Projects in Concept Schematics If you wish to create a hierarchical design that contains symbols representing other MAX+PLUS II-supported design files, such as Altera® Hardware Description Language (AHDL) Text Design Files (.tdf), you can create a hollow-body symbol that represents a design file and then instantiate it in your Concept schematic. To create a hierarchical project in your Concept schematic, go through the following steps: Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS® II/Cadence Working Environment. Create a Concept schematic and save it in your working directory, as described in Creating Concept Schematics for Use with MAX+PLUS II Software. You can instantiate MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support. Create the hollow-body symbol <design name> in Concept by typing the following command from the <working directory>/source directory that contains the lower-level design file <design name>.<extension>: concept <design name>.body Create a part file to indicate that the body is hollow: Add the DEFINE and DRAWING bodies to the part drawing. These bodies should be the only two bodies in the drawing. Add the TITLE=<design name> and the ABBREV=<design name> properties to the DRAWING body to identify the drawing. Save the part drawing with the name <design name>.part.1.1. Regardless of the hardware description language (HDL) or schematic editor used to create the design, you must create a dummy Verilog HDL module to indicate to the concept2alt utility that the design is a "black box" that must pass untouched through the EDIF netlist file. Type genview verilog in the Concept window. Type logic when prompted for the Verilog View name. If you are using VerilogLink, you must type genview verilog again, then type verilog_lib when prompted for the Verilog View name. Type cd <design name>/logic at the UNIX prompt from the /source directory to change to the /source/<design name>/logic directory. Edit the verilog.v file to add the cds_action = "ignore" parameter setting after the Input Declarations and Output Declarations sections. This parameter setting specifies that the <design name> should be treated as a "black box." To enter the symbol in the higher-level Concept schematic, choose the Add Part button, choose the name of the working SCALD directory, then choose the <design name> symbol from the Symbol menu. The MAX+PLUS II software uses the cadence.lmf Library Mapping File to map Concept symbols to equivalent MAX+PLUS II logic functions. To use custom symbols, you must create a custom LMF that maps your custom symbols to the equivalent EDIF Input File, Text Design File (TDF), or other design file. You will also need to specify this custom LMF in the EDIF Netlist Reader Settings dialog box before compiling with the MAX+PLUS II software. See Compiling Projects with MAX+PLUS II Software for more information. Continue with the steps necessary to complete your Concept schematic, as described in Creating Concept Schematics for Use with MAX+PLUS II Software. Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample hierarchical AHDL and Concept schematic file: /usr/maxplus2/examples/cadence/example4/fulladd2 Converting Concept Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the concept2alt Utility You can use the concept2alt utility to generate an EDIF netlist file from a Concept schematic. This file can then be imported into the MAX+PLUS® II software as an EDIF Input File (.edf). To convert a Concept schematic into an EDIF netlist file, follow these steps: Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment. Create a Concept schematic and save it in your working directory, as described in Creating Concept Schematics for Use with MAX+PLUS II Software. You can instantiate MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support. Type the following command at the UNIX prompt from the /source directory that contains the schematic: concept2alt -rundir ../max2 <design name> If your design uses library of parameterized modules (LPM) functions, you must also include the -family option. For example: concept2 alt -family FLEX10K -rundirmax2 <design name> Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software. Creating Composer Schematics for Use with MAX+PLUS II Software You can create Composer schematics and convert them into EDIF Input Files (.edf) that can be processed with the MAX+PLUS® II Compiler. To create a Composer schematic for use with the MAX+PLUS II software, follow these steps: Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment. Start the Composer schematic editor from the <working directory> by typing icds at a UNIX prompt. Use the graphical user interface to structure and organize your files to create an environment that facilitates entering and processing designs. Go to Composer Project File Directory Structure for more information on directories in Composer. Choose Library Path Editor (Tools menu) to create the <design name> library. In the Library dialog box, type <project directory name> as the Library name and ./source/<design name> as the Path name. Choose Save (File menu), then choose Exit (File menu) to save the path. Choose Library Manager (Tools menu) to start Composer and create a new design. Type <project directory name> as the Library name, <design name> as the Cell name, and schematic as the View name in the Library Manager dialog box and press the key. Enter primitives, megafunctions, and macrofunctions from the following libraries: MAX+PLUS II-compatible primitives, megafunctions, and macrofunctions are available in the Altera-provided alt_max2 component library. Input, output, and bidirectional pins are available in the Cadence basic library located under /cadence/etc/cdslib. MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support. If you wish to create a hierarchical design that contains symbols representing other design files, such as Altera® Hardware Description Language (AHDL) Text Design Files, go to Creating Hierarchical Projects in Composer Schematics. Enter meaningful instance names for all symbols and functions so that you can easily trace internal node names during simulation and debugging operations. For example, if an a161 macrofunction is instantiated several times in one design, you should define a unique name for each instance. The instance name for each symbol is controlled by INST property. For more information on assigning properties, refer to the Cadence Composer User Guide. (Optional) To enter resource assignments in your Composer schematic, go to Entering Resource Assignments. You can also enter resource assignments from within the MAX+PLUS II software. (Optional) Functionally simulate the design with the Verilog-XL simulator. Altera provides Verilog HDL simulation modules in the /usr/maxplus2/simlib/composer/alt_max2/verilog and /usr/maxplus2/simlib/composer/alt_max2/verilogUdps directories. Go to Performing a Functional Simulation of a Composer Schematic with Verilog-XL Software for more information. Use the altout utility to generate an EDIF netlist file that can be imported into the MAX+PLUS II software, as described in Converting Composer Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the altout Utility. Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software. Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample Composer schematic files: /usr/maxplus2/examples/cadence/example2/fulladd /usr/maxplus2/examples/cadence/example5/fulladd2 /usr/maxplus2/examples/cadence/example7/fa2 Entering Resource Assignments The MAX+PLUS® II software allows you to enter a variety of resource and device assignments for your projects. Resource assignments are used to assign logic functions to a particular pin, logic cell, I/O cell, embedded cell, row, column, Logic Array Block (LAB), Embedded Array Block (EAB), chip, clique, local routing, logic option, timing requirement, or connected pin group. In MAX+PLUS II software, you can enter all types of resource and device assignments with Assign menu commands. You can also enter pin, logic cell, I/O cell, embedded cell, LAB, EAB, row, and column assignments in the MAX+PLUS II Floorplan Editor. The Assign menu commands and the Floorplan Editor all save assignment information in the ASCII Assignment & Configuration File (.acf) for the project. In addition, you can edit ACFs manually in any standard text editor or with the setacf utility. Concept & Composer Schematics In both Concept and Composer schematics, you can assign a limited subset of these resource assignments by assigning properties to symbols. These properties are incorporated into the EDIF netlist file(s). The MAX+PLUS II software automatically converts assignment information from the EDIF Input File into the ACF format. For information on making MAX+PLUS II-compatible resource assignments, go to the following topics: Assigning Pins, Logic Cells & Chips Assigning Cliques Assigning Logic Options Modifying the Assignment & Configuration File with the setacf Utility Go to the Cadence Concept Schematic User Guide and Composer Reference User Guide for details on how to assign properties. Go to "Resource Assignments in EDIF Input Files" and "Assigning Resources in a Third-Party Design Editor" in MAX+PLUS II Help for more information on assignments or properties that can be assigned in Concept and Composer. Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample Concept and Composer schematic files, which include resource assignments: /usr/maxplus2/examples/cadence/example6/fa2 (Concept) /usr/maxplus2/examples/cadence/example7/fa2 (Composer) VHDL & Verilog HDL Design Files For Verilog HDL- and VHDL-based designs, you must use the MAX+PLUS II software or the setacf utility to enter resource assignments. For information on using the setacf utility, go to Modifying the Assignment & Configuration File with the setacf Utility. For information on entering assignments in the MAX+PLUS II software with Assign menu commands or in an ACF, go to "resource assignments" or "ACF, format" in MAX+PLUS II Help using Search for Help on (Help menu). Assigning Pins, Logic Cells & Chips You can assign a single logic function to a specific pin or logic cell (including I/O cells and embedded cells) within a chip, and assign one or more functions to a specific chip. A chip is a group of logic functions defined as a single, named unit, which can be assigned to a specific device. You can assign a signal to a particular pin to ensure that the signal is always associated with that pin, regardless of future changes to the project. If you wish to set and maintain the performance of your project, assigning logic to a specific logic cell within a chip can minimize timing delays. In a project that is partitioned among multiple devices, you can assign logic functions that must be kept together in the same device to a chip. Chip assignments allow you to split a project so that only a minimum number of signals travel between devices, and to ensure that no unnecessary device-to-device delays exist on critical timing paths. You can assign a chip to a device in some EDA tools or in the MAX+PLUS® II software. Use the following syntax for chip, pin, and logic cell assignments: To assign a logic function to a chip: CHIP_PIN_LC=<chip name> For example: CHIP_PIN_LC=chip1 To assign a pin number within a chip: CHIP_PIN_LC=<chip name>@<pin number> For example: CHIP_PIN_LC=chip1@K2 To assign a logic cell, I/O cell, or embedded cell number: CHIP_PIN_LC=<chip name>@LC<logic cell number> CHIP_PIN_LC=<chip name>@IOC<I/O cell number> CHIP_PIN_LC=<chip name>@EC<embedded cell number> For example: CHIP_PIN_LC=chip1@LC44 Related Topics: Refer to the following sources for additional information: To assign a clique, use the following syntax: CLIQUE=<clique name> For example: CLIQUE=fast1 Related Topics: Go to the following topics in MAX+PLUS II Help for related information: Assigning a Clique Guidelines for Achieving Maximum Speed Performance Assigning Logic Options Logic option and logic synthesis style assignments allow you to guide logic synthesis with logic optimization features that are specific to Altera® devices. You can assign logic options and styles to individual logic functions in your design. The MAX+PLUS® II Compiler also uses a device-family-specific default logic synthesis style for each project. Related Topics: Go to "Resource Assignments in EDIF Input Files" and "Assigning Resources in a Third-Party Design Editor" in MAX+PLUS II Help for complete and up-to-date information on logic option and logic synthesis style assignments, including definitions and syntax of these assignments. You can instantiate MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support. Create the hollow-body symbol <design name> in Composer by typing icds from the <working directory> at the UNIX prompt. Choose Library Path Editor (Tools menu) to create the <design name> library. Type <design name> as the Library name and ./source/<design name> as the Path name. Choose Save (File menu), then choose Exit (File menu) to save the path and exit from the Library Path Editor. Choose Library Manager (Tools menu) to start Composer and create a symbol for your design. Type <project directory name> as the Library name, <lower-level design name> as the Cell name, symbol as the View name, and then press . Create a hollow-body symbol that represents the inputs and outputs of your design. Enter input and output pins for the symbol. Save the symbol. To enter the symbol in your higher-level schematic design, choose the Component button and type <project directory name> as the Library name, <lower-level design name> as the Cell name, and symbol as the View name. The MAX+PLUS II software uses the cadence.lmf Library Mapping File to map Concept symbols to equivalent MAX+PLUS II logic functions. To use custom symbols, you must create a custom LMF that maps your custom symbols to the equivalent EDIF Input File, Text Design File (TDF), or other design file. You will also need to specify this custom LMF in the EDIF Netlist Reader Settings dialog box before compiling with the MAX+PLUS II software. See Compiling Projects with MAX+PLUS II Software for more information. Continue with the steps necessary to complete your Composer schematic, as described in Creating Composer Schematics for Use with MAX+PLUS II Software. Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample hierarchical AHDL and Composer schematic file: /usr/maxplus2/examples/cadence/example5/fulladd2 Converting Composer Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the altout Utility You can use the altout utility to generate an EDIF netlist file from a Composer schematic. This file can then be imported into the MAX+PLUS® II software as an EDIF Input File (.edf). To convert Composer schematics into MAX+PLUS II-compatible EDIF netlist files, follow these steps: Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment. Create a Composer schematic and save it in your working directory, as described in Creating Composer Schematics for Use with MAX+PLUS II Software. You can instantiate MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support. Type the following command at the UNIX prompt from the working directory that contains the schematic: altout -lib <design name> -rundir max2 <design name> Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software. Creating VHDL Designs for Use with MAX+PLUS II Software You can create VHDL design files with the MAX+PLUS® II Text Editor or another standard text editor and save them in the appropriate directory for your project. The MAX+PLUS II Text Editor offers the following advantages: VHDL templates are available with the VHDL Templates command (Templates menu). These templates are also available in the ASCII vhdl.tmp file, which is located in the /usr/maxplus2 directory. If you use the MAX+PLUS II Text Editor to create your VHDL design, you can use the Syntax Coloring command (Options menu). The Syntax Coloring feature displays keywords and other elements in text files in different colors to distinguish them from other forms of syntax. To create a VHDL design that can be synthesized and optimized with Synergy software, follow these steps: You can instantiate the following MAX+PLUS II-provided logic functions in your VHDL design: The alt_mf library contains the Altera® VHDL logic function library, which includes the a_8count, a_8mcomp, a_8fadd, and a_81mux macrofunctions. If you wish to instantiate alt_mf logic functions in your VHDL design, you must first compile this library, as described in Compiling the alt_mf Library. The clklock megafunction, which enables the phase-locked loop, or ClockLock™, circuitry available on selected Altera FLEX® 10K devices. Go to Instantiating the clklock Megafunction in VHDL or Verilog HDL for information. MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support. If you wish to use Standard Delay Format (SDF) Output Files (.sdo) that contain timing information when performing post-compilation timing simulation with Leapfrog software, you must first compile the VITAL library source files, as described in Compiling the alt_vtl Library for for Use with Leapfrog Software. (Optional) To enter resource assignments in your VHDL design, go to Entering Resource Assignments. You can also enter resource assignments from within the MAX+PLUS II software. After you have completed your VHDL design, synthesize and optimize it with Synergy software, as described in Synthesizing & Optimizing VHDL Files with Synergy Software. Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample VHDL files, the latter of which includes macrofunction instantiation. /usr/maxplus2/examples/cadence/example9/count4.vhd /usr/maxplus2/examples/cadence/example10/adder16.vhd Related Topics: Go to FLEX 10K Device Family, which is available on the web, for additional information. Instantiating the clklock Megafunction in VHDL or Verilog HDL MAX+PLUS® II interfaces to other EDA tools support the clklock phase-locked loop megafunction, which can be used with some FLEX® 10K devices, with the gencklk utility, which is available in the MAX+PLUS II system directory. Type gencklk -h at the DOS or UNIX prompt to display information on how to use this utility. The gencklk utility generates VHDL or Verilog HDL functional simulation models and a VHDL Component Declaration template file (.cmp). The gencklk utility allows parameters for the clklock function to be passed from the VHDL or Verilog HDL file to EDIF netlist format. The gencklk utility embeds the parameter values in the clklock function name; therefore, the values do not need to be declared explicitly. To instantiate the clklock megafunction in VHDL or Verilog HDL, go through the following steps: Type the following command at the DOS or UNIX prompt to generate the clklock_x_y function, where x is the ClockBoost™ value and y is the input frequency in MHz: Type gencklk <ClockBoost> <input frequency> -vhdl for VHDL designs. or: Type gencklk <ClockBoost> <input frequency> -verilog for Verilog HDL designs. Choose Megafunctions/LPM from the MAX+PLUS II Help menu for more information on the clklock megafunction. Create a design file that instantiates the clklock_x_y.vhd or clklock_x_y.v file. The gencklk utility automatically generates a VHDL Component Declaration template in the clklock_x_y.cmp file that you can incorporate into a VHDL design file. In MAX+PLUS II version 8.3 and lower, running genclklk on a PC always creates files named as clklock.vhd, clklock.cmp, and clklock.v, regardless of the ClockBoost and input frequency values you specify. Figures 1 and 2 show a clklock function with <ClockBoost> = 2 and <input frequency> = 40 MHz instantiated in VHDL and Verilog HDL design files, respectively. Figure 1. VHDL Design File with clklock Instantiation (count8.vhd) LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera; USE altera.maxplus2.all; -- Include Altera Component Declarations ENTITY count8 IS PORT (a : IN STD_LOGIC_VECTOR(7 DOWNTO 0); ldn : IN STD_LOGIC; gn : IN STD_LOGIC; dnup : IN STD_LOGIC; setn : IN STD_LOGIC; clrn : IN STD_LOGIC; clk : IN STD_LOGIC; co : OUT STD_LOGIC; q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END count8; ARCHITECTURE structure OF count8 IS signal clk2x : STD_LOGIC; COMPONENT clklock_2_40 PORT ( INCLK : IN STD_LOGIC; OUTCLK : OUT STD_LOGIC ); END COMPONENT; BEGIN u1: clklock_2_40 PORT MAP (inclk=>clk, outclk=>clk2x); u2: a_8count PORT MAP (a=>a(0), b=>a(1), c=>a(2), d=>a(3), e=>a(4), f=>a(5), g=>a(6), h=>a(7), clk=>clk2x, ldn=>ldn, gn=>gn, dnup=>dnup, setn=>setn, clrn=>clrn, qa=>q(0), qb=>q(1), qc=>q(2), qd=>q(3), qe=>q(4), qf=>q(5), qg=>q(6), qh=>q(7), cout=>co); END structure; Figure 2. Verilog HDL Design File with clklock Instantiation (count8.v) `timescale 1ns / 10ps module count8 (a, ldn, gn, dnup, setn, clrn, clk, co, q); output co; output[7:0] q; input[7:0] a; input ldn, gn,dnup, setn, clrn, clk; wire clk2x; clklock_2_40 u1 (.inclk(clk), .outclk(clk2x) ); A_8COUNT u2 (.A(a[0]), .B(a[1]), .C(a[2]), .D(a[3]), .E(a[4]), .F(a[5]), .G(a[6]), .H(a[7]), .LDN(ldn), .GN(gn), .DNUP(dnup), .SETN(setn), .CLRN(clrn), .CLK(clk2x), .QA(q[0]), .QB(q[1]), .QC(q[2]), .QD(q[3]), .QE(q[4]), .QF(q[5]), .QG(q[6]), .QH(q[7]), .COUT(co) ); endmodule Related Topics: Go to FLEX 10K Device Family, which is available on the web, for additional information. Entering Resource Assignments The MAX+PLUS® II software allows you to enter a variety of resource and device assignments for your projects. Resource assignments are used to assign logic functions to a particular pin, logic cell, I/O cell, embedded cell, row, column, Logic Array Block (LAB), Embedded Array Block (EAB), chip, clique, local routing, logic option, timing requirement, or connected pin group. In MAX+PLUS II software, you can enter all types of resource and device assignments with Assign menu commands. You can also enter pin, logic cell, I/O cell, embedded cell, LAB, EAB, row, and column assignments in the MAX+PLUS II Floorplan Editor. The Assign menu commands and the Floorplan Editor all save assignment information in the ASCII Assignment & Configuration File (.acf) for the project. In addition, you can edit ACFs manually in any standard text editor or with the setacf utility. Concept & Composer Schematics In both Concept and Composer schematics, you can assign a limited subset of these resource assignments by assigning properties to symbols. These properties are incorporated into the EDIF netlist file(s). The MAX+PLUS II software automatically converts assignment information from the EDIF Input File into the ACF format. For information on making MAX+PLUS II-compatible resource assignments, go to the following topics: Assigning Pins, Logic Cells & Chips Assigning Cliques Assigning Logic Options Modifying the Assignment & Configuration File with the setacf Utility Go to the Cadence Concept Schematic User Guide and Composer Reference User Guide for details on how to assign properties. Go to "Resource Assignments in EDIF Input Files" and "Assigning Resources in a Third-Party Design Editor" in MAX+PLUS II Help for more information on assignments or properties that can be assigned in Concept and Composer. Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample Concept and Composer schematic files, which include resource assignments: /usr/maxplus2/examples/cadence/example6/fa2 (Concept) /usr/maxplus2/examples/cadence/example7/fa2 (Composer) VHDL & Verilog HDL Design Files For Verilog HDL- and VHDL-based designs, you must use the MAX+PLUS II software or the setacf utility to enter resource assignments. For information on using the setacf utility, go to Modifying the Assignment & Configuration File with the setacf Utility. For information on entering assignments in the MAX+PLUS II software with Assign menu commands or in an ACF, go to "resource assignments" or "ACF, format" in MAX+PLUS II Help using Search for Help on (Help menu).