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主页 > 支持 > 软件 > Using Cadence Tools with MAX+PLUS II Software 打印此页 发送此页 Using Cadence Tools with MAX+PLUS II Software The following topics describe how to use a variety of Cadence tools as part of a complete design flow that includes the MAX+PLUS® II software. If you use only one Cadence tool, click List by Tool and select the tool name to view the list of topics only for that tool. Click on one of the following topics for information: Open a printable version of all topics listed on this page. Setting Up the MAX+PLUS II/Cadence Working Environment Software Requirements Setting Up the MAX+PLUS II/Cadence Concept Work Environment for a Sun SPARCstation Running SunOS Software MAX+PLUS II/Cadence Interface File Organization MAX+PLUS II Directory Structure Concept & RapidSIM Local Work Area Directory Structure Concept & HDL Direct Project Directory Structure Composer Project File Directory Structure Altera-Provided Logic & Symbol Libraries Compiling the VITAL Library for Use with Leapfrog Software Compiling the alt_mf Library Design Flow for All Cadence Tools Design Entry Design Entry Flow Concept Creating Concept Schematics for Use with MAX+PLUS II Software Instantiating the clklock Megafunction in Concept Schematics Instantiating LPM & Other Parameterized Functions in Concept Schematics Entering Resource Assignments Assigning Pins, Logic Cells & Chips Assigning Cliques Assigning Logic Options Modifying the Assignment & Configuration File with the setacf Utility Performing a Functional Simulation of a Concept Schematic with the hdlconfig Utility & Verilog-XL Software Performing a Functional Simulation of a Concept Schematic with VerilogLink & Verilog-XL Software Creating Hierarchical Projects in Concept Schematics Converting Concept Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the concept2alt Utility Composer Creating Composer Schematics for Use with MAX+PLUS II Software Entering Resource Assignments Assigning Pins, Logic Cells & Chips Assigning Cliques Assigning Logic Options Modifying the Assignment & Configuration File with the setacf Utility Performing a Functional Simulation of a Composer Schematic with Verilog-XL Software Creating Hierarchical Projects in Composer Schematics Converting Composer Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the altout Utility VHDL Creating VHDL Designs for Use with MAX+PLUS II Software Instantiating the clklock Megafunction in VHDL or Verilog HDL Entering Resource Assignments Modifying the Assignment & Configuration File with the setacf Utility Verilog HDL Creating Verilog HDL Designs for Use with MAX+PLUS II Software Instantiating the clklock Megafunction in VHDL or Verilog HDL Entering Resource Assignments Modifying the Assignment & Configuration File with the setacf Utility Synthesis & Optimization VHDL Synthesizing & Optimizing VHDL Files with Synergy Software Converting VHDL Designs into MAX+PLUS II-Compatible EDIF Netlist Files with the vlog2alt or altout Utility Verilog HDL Synthesizing & Optimizing Verilog HDL Files with Synergy Software Converting Verilog HDL Designs into MAX+PLUS II-Compatible EDIF Netlist Files with the vlog2alt Utility Compilation Project Compilation Flow Compiling Projects with MAX+PLUS II Software Simulation Project Simulation Flow Initializing Registers in VHDL & Verilog Output Files for Power-Up before Simulation Performing a Timing Simulation with RapidSIM Software Performing a Timing Simulation with Verilog-XL Software Performing a Timing Simulation with Leapfrog Software Compiling the VITAL Library for Use with Leapfrog Software Compiling the alt_mf Library Device Programming Programming Altera Devices Related Links: MAX+PLUS II Development Software Altera Programming Hardware Cadence web site (http://www.cadence.com) Feedback Did this information help you? If no, please log onto mySupport to file a technical request or enhancement. Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution. 给本页评分

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