Performing a Timing Simulation with Leapfrog Software
Once the
MAX+PLUS® II software has compiled a project and generated a VHDL Output File (.vho), you can a perform timing simulation using Cadence Leapfrog software.
To simulate a VHDL output file with the Leapfrog timing simulator, follow these steps:
- Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment.
- If you wish to use MAX+PLUS II-generated Standard Delay Format (SDF) Output Files (.sdo) that contain timing information, compile the VITAL library source files, as described in Compiling the VITAL Library for Use with Leapfrog Software.
- If your design uses functions from the alt_mf library, compile the library, as described in Compiling the alt_mf Library.
- Generate a VHDL Output File (.vho) and an optional SDF Output File, as described in Compiling Projects with MAX+PLUS II Software.
- Using any standard text editor, create a stimulus file that includes test vectors for <design name>.
- Start the Leapfrog simulator and simulate the MAX+PLUS II-created VHDL Output File <design name>.vho by typing
leapfrog  at the UNIX prompt. Refer to Chapter 5: SDF Back-Annotation in Leapfrog in the VHDL Simulator User Guide or refer to the Cadence Openbook for more information.
<<<<<<< leapfrog.htm
Technical Feedback
=======
Feedback
>>>>>>> 1.7
Did this information help you?
If no, please log onto mySupport to file a technical request or enhancement.
Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
|
文档资料
> 
