Converting VHDL Designs into MAX+PLUS II-Compatible EDIF Netlist Files with the vlog2alt or altout Utility
You can convert a VHDL design into an EDIF netlist file with the extension .edf. This file can then be imported into the
MAX+PLUS® II software as an EDIF Input File (.edf).
To convert a VHDL design into an EDIF netlist file, follow these steps:
- Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment.
- Synthesize and optimize your VHDL design with Synergy, as described in Synthesizing & Optimizing VHDL Files with Synergy Software.
- Depending on whether or not you have installed the Concept alt_syn library, perform one of the following steps to create <design name>.edf in the working directory:
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If you have installed the Concept alt_syn library, type the following command at the UNIX prompt from your working directory:
vlog2alt <design name> -rundir max2 -vfiles <design name>.run1/syn.v 
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or:
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If you have not installed the Concept alt_syn library, follow these steps: |
- Edit the cds.lib file, which is located in your working directory, to include the following line:
DEFINE Opt <working directory>/<design name>.run1/Opt
- Type the following command at the UNIX prompt from the working directory:
altout -lib Opt -rundir max2 <design name>
- Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.
Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample VHDL files:
- /usr/maxplus2/examples/cadence/example9/count4.vhd
- /usr/maxplus2/examples/cadence/example10/adder16.vhd
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Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
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