文档资料 许可 在线购买 下载 全部页面 技术资料 产品型号

主页   |   产品   |   支持   |   最终市场   |   技术中心   |   教育与活动   |   公司介绍   |   在线购买

mySupport   |   器件   |   软件   |   IP   |   设计范例   |   参考设计

产品    Quartus II       SOPC Builder       MAX+PLUS II       ModelSim-Altera     资源中心       简介       安装&许可       脚本        电路板设计& I/O       网表阅读器 & 综合       编译增强特性       优化       功耗管理    TimeQuest时序分析器       标准时序分析器       仿真 & 确认       片内调试       HardCopy设计     软件资源       操作系统支持       驱动安装     下载与许可       下载    许可     Quartus II EDA 支持       Quartus II 接口    综合工具    仿真工具    验证工具    时序分析工具    再综合工具    电路板级工具     老版软件EDA支持       供应商类       工具类       功能类

主页 > 支持 > 软件 > Performing a Timing Simulation with Verilog-XL Software 打印此页 发送此页 Performing a Timing Simulation with Verilog-XL Software Once the MAX+PLUS® II software has compiled a project and generated a Verilog Output File (.vo), you can perform a timing simulation using Cadence Verilog-XL software. To simulate Verilog output files with the Verilog-XL timing simulator, follow these steps: Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment. Generate Verilog Output Files (.vo), as described in Compiling Projects with MAX+PLUS II Software. The MAX+PLUS II Compiler generates the <design name>.vo and alt_max2.vo files for use with Verilog-XL software. Using any standard text editor, create a stimulus file that includes test vectors for your design. Start the Verilog-XL simulator and simulate your Verilog output files by typing the following command at the UNIX prompt: verilog <stimulus filename(s)> <design name> alt_max2.vo Feedback Did this information help you? If no, please log onto mySupport to file a technical request or enhancement. Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution. 给本页评分

请填写反馈意见   注册索取最新邮件通知

主页 | 产品 | 支持 | 最终市场 | 技术中心 | 教育与活动 | 公司介绍 | 在线购买  mySupport | 器件 | 软件 | IP | 设计范例 | 参考设计  联系我们 | 站点帮助 | 网站导航 | 个人信息 | 法律申明  Copyright © 1995-2008 Altera International Limited, 香港九龙观塘观塘道388号创纪之城1期1座9楼11-18室 Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus和MegaCore是Altera公司的商标。