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主页 > 支持 > 软件 > Using Cadence Verilog-XL & MAX+PLUS II Software 打印此页 发送此页 Using Cadence Verilog-XL & MAX+PLUS II Software The following topics describe how to use the Cadence Verilog-XL software with MAX+PLUS® II software. Choose one of the following topics for information: Open a printable version of all topics listed on this page. Setting Up the MAX+PLUS II/Cadence Working Environment Software Requirements MAX+PLUS II Directory Structure MAX+PLUS II/Cadence Interface File Organization Functional Simulation Performing a Functional Simulation of a Concept Schematic with the hdlconfig Utility & Verilog-XL Software Performing a Functional Simulation of a Concept Schematic with VerilogLink & Verilog-XL Software Timing Simulation Project Simulation Flow Initializing Registers in VHDL & Verilog Output Files for Power-Up before Simulation Performing a Timing Simulation with Verilog-XL Software Related Links: Go to the following MAX+PLUS II ACCESSSM Key topics for related information: Using Cadence Concept & MAX+PLUS II Software Compiling Projects with MAX+PLUS II Software Programming Altera Devices Go to the following topics, which are available on the web, for additional information: MAX+PLUS II Development Software Altera Programming Hardware Cadence web site (http://www.cadence.com) Feedback Did this information help you? If no, please log onto mySupport to file a technical request or enhancement. Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution. 给本页评分

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