Instantiating the clklock Megafunction in VHDL or Verilog HDL
MAX+PLUS® II interfaces to other EDA tools support the clklock phase-locked loop megafunction, which can be used with some FLEX® 10K devices, with the gencklk utility. Type gencklk -h  at the DOS or UNIX prompt to display information on how to use this utility. The gencklk utility generates VHDL or Verilog HDL functional simulation models and a VHDL Component Declaration template file (.cmp).
The gencklk utility allows parameters for the clklock function to be passed from the VHDL or Verilog HDL file to EDIF netlist format. The gencklk utility embeds the parameter values in the clklock function name; therefore, the values do not need to be declared explicitly.
To instantiate the clklock megafunction in VHDL or Verilog HDL, go through the following steps:
- Type the following command at the DOS or UNIX prompt to generate the
clklock_x_y function, where x is the ClockBoost™ value and y is the input frequency in MHz:
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Type gencklk <ClockBoost> <input frequency> -vhdl for VHDL designs. |
or:
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Type gencklk <ClockBoost> <input frequency> -verilog for Verilog HDL designs. |
Choose Megafunctions/LPM from the MAX+PLUS II Help menu for more information on the clklock megafunction.
- Create a design file that instantiates the
clklock_x_y.vhd or clklock_x_y.v file. The gencklk utility automatically generates a VHDL Component Declaration template in the clklock_x_y.cmp file that you can incorporate into a VHDL design file.
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In MAX+PLUS II version 8.3 and lower, running genclklk on a PC always creates files named as clklock.vhd, clklock.cmp, and clklock.v, regardless of the ClockBoost and input frequency values you specify. |
Figures 1 and 2 show a clklock function with <ClockBoost> = 2 and <input frequency> = 40 MHz instantiated in VHDL and Verilog HDL design files, respectively.
| Figure 1. VHDL Design File with clklock Instantiation (count8.vhd) |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera;
USE altera.maxplus2.all; -- Include Altera Component Declarations
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ENTITY count8 IS
PORT (a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ldn : IN STD_LOGIC;
gn : IN STD_LOGIC;
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dnup : IN STD_LOGIC;
setn : IN STD_LOGIC;
clrn : IN STD_LOGIC;
clk : IN STD_LOGIC;
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co : OUT STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END count8;
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ARCHITECTURE structure OF count8 IS
signal clk2x : STD_LOGIC;
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COMPONENT clklock_2_40
PORT (
INCLK : IN STD_LOGIC;
OUTCLK : OUT STD_LOGIC
);
END COMPONENT;
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BEGIN
u1: clklock_2_40
PORT MAP (inclk=>clk, outclk=>clk2x);
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u2: a_8count
PORT MAP (a=>a(0), b=>a(1), c=>a(2), d=>a(3),
e=>a(4), f=>a(5), g=>a(6), h=>a(7),
clk=>clk2x,
ldn=>ldn,
gn=>gn,
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dnup=>dnup,
setn=>setn,
clrn=>clrn,
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qa=>q(0), qb=>q(1), qc=>q(2), qd=>q(3),
qe=>q(4), qf=>q(5), qg=>q(6), qh=>q(7),
cout=>co);
END structure;
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| Figure 2. Verilog HDL Design File with clklock Instantiation (count8.v) |
`timescale 1ns / 10ps
module count8 (a, ldn, gn, dnup, setn, clrn, clk, co, q);
output co;
output[7:0] q;
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input[7:0] a;
input ldn, gn,dnup, setn, clrn, clk;
wire clk2x;
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clklock_2_40 u1 (.inclk(clk), .outclk(clk2x) );
A_8COUNT u2 (.A(a[0]), .B(a[1]), .C(a[2]), .D(a[3]), .E(a[4]), .F(a[5]),
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.G(a[6]), .H(a[7]), .LDN(ldn), .GN(gn), .DNUP(dnup),
.SETN(setn), .CLRN(clrn), .CLK(clk2x), .QA(q[0]), .QB(q[1]),
.QC(q[2]), .QD(q[3]), .QE(q[4]), .QF(q[5]), .QG(q[6]),
.QH(q[7]), .COUT(co) );
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endmodule
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