Initializing Registers in VHDL & Verilog Output Files for Power-Up before Simulation
Altera provides the add_dc script, which is availiable in the MAX+PLUS II system directory, to allow you to process MAX+PLUS II-generated Verilog Output Files (.vo) and VHDL Output Files (.vho) to prepare these files for simulation with another EDA tool. The add_dc script runs the add_dclr utility, which inserts a device_clear signal that is used for power-up initialization of all registers or flipflops in the design.
The script adds in a top-level signal named device_clear and connects it to the CLRN pin in all flipflops that should initialize to 0, and to the PRN pin of all flipflops that should initialize to 1. If the CLRN or PRN pin of a flipflop is already being used (i.e., is already connected to a signal), the script modifies the Verilog Output File or VHDL Output File so that the AND of the original signal and the device_clear pin feed the CLRN or PRN pin.
To use the add_dc script to process Verilog Output Files and VHDL Output Files before simulation with another EDA tool, follow these steps:
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Make sure that your design file is located in the current directory, or change to the directory in which the design file is located.
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Type the following command at the command prompt:
Â¥<path name of add_dc.bat file>Â¥add_dc <design name> <path name of add_dclr.exe file> 
For example, if the both the add_dc.bat and the add_dclr.exe files are located in the d:Â¥maxplus2Â¥exew directory, and the d:Â¥maxplus2Â¥exew directory is specified in the search path, you can type the following command at a command prompt to add a device_clear signal to a design named myfifo in the file myfifo.vo:
add_dc myfifo d:Â¥maxplus2Â¥exew
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The add_dc script gives a message if the directory contains both a VHDL Output File and a Verilog Output File with the same name (<design name>.vo and <design>.vho). You should delete or rename whichever of those files should not have the device_clear signal added. The add_dc script can modify only one design file at a time.
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When the add_dc script processes the Verilog Output File or VHDL Output File, it creates a backup copy of the original file, with the extension .ori.
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The add_dc script works only for Verilog Output Files and VHDL Output Files that are generated by MAX+PLUS II.
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After you have used the add_dc script and are ready to simulate the resulting Verilog Output File or VHDL Output File with another EDA tool, you should assert the active low device_clear pin for a period of time that is long enough for the design to initialize. You can then de-assert the pin, and apply simulation vectors to the design.
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Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
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