文档资料 许可 在线购买 下载 全部页面 技术资料 产品型号

主页   |   产品   |   支持   |   最终市场   |   技术中心   |   教育与活动   |   公司介绍   |   在线购买

mySupport   |   器件   |   软件   |   IP   |   设计范例   |   参考设计

产品    Quartus II       SOPC Builder       MAX+PLUS II       ModelSim-Altera     资源中心       简介       安装&许可       脚本        电路板设计& I/O       网表阅读器 & 综合       编译增强特性       优化       功耗管理    TimeQuest时序分析器       标准时序分析器       仿真 & 确认       片内调试       HardCopy设计     软件资源       操作系统支持       驱动安装     下载与许可       下载    许可     Quartus II EDA 支持       Quartus II 接口    综合工具    仿真工具    验证工具    时序分析工具    再综合工具    电路板级工具     老版软件EDA支持       供应商类       工具类       功能类

主页 > 支持 > 软件 > Using Mentor Graphics & Exemplar Logic Tools with MAX+PLUS II Software 打印此页 发送此页 Using Mentor Graphics & Exemplar Logic Tools with MAX+PLUS II Software The following topics describe how to use a variety of Mentor Graphics and Exemplar Logic tools as part of a complete design flow that includes the MAX+PLUS® II software. If you use only one Mentor Graphics or Exemplar Logic tool, click List by Tool and select the tool name to view the list of topics only for that tool. Click on one of the following topics for information: Open a printable version of all topics listed on this page. Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment Software Requirements Altera-Provided Logic & Symbol Libraries Local Work Area Directory Structure Mentor Graphics Project Directory Structure MAX+PLUS II Project Directory Structure MAX+PLUS II/Mentor Graphics/Exemplar Logic Interface File Organization Design Flow For All Mentor Graphics/Exemplar Logic Tools Design Entry Design Entry Flow Design Architect Creating Design Architect Schematics for Use with MAX+PLUS II Software Instantiating the clklock Megafunction in Design Architect Schematics Instantiating LPM Functions in Design Architect Schematics Entering Resource Assignments Assigning Pins, Logic Cells & Chips Assigning Cliques Assigning Logic Options Modifying the Assignment & Configuration File with the setacf Utility Back­Annotating MAX+PLUS II Pin Assignments to Design Architect Symbols Creating Hierarchical Projects with Design Architect Software Performing a Functional Simulation with DVE & QuickSim II Software Performing a Functional Simulation with QuickHDL Pro Software Converting Design Architect Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the ENWrite Utility VHDL & Verilog HDL Creating VHDL & Verilog HDL Designs for Use with MAX+PLUS II Software Instantiating the clklock Megafunction in VHDL or Verilog HDL Instantiating LPM Functions in VHDL Entering Resource Assignments Modifying the Assignment & Configuration File with the setacf Utility Performing a Functional Simulation with QuickHDL Software Performing a Functional Simulation with QuickHDL Pro Software Creating Hierarchical Projects with Design Architect Software Synthesis & Optimization Synthesizing & Optimizing VHDL & Verilog HDL Projects with Galileo Extreme Software Synthesizing & Optimizing VHDL & Verilog HDL Projects with Leonardo Software Compilation Project Compilation Flow Compiling Projects with MAX+PLUS II Software Exemplar Logic Galileo Extreme­Specific Compiler Settings Using the Altera Schematic Express (sch_exprss) Utility Using the Altera VHDL Express (vhd_exprss) Utility Back­Annotation Back­Annotating MAX+PLUS II Pin Assignments to Design Architect Symbols Simulation/Timing Analysis Project Simulation/Timing Analysis Flow Initializing Registers in VHDL & Verilog Output Files for Power-Up before Simulation Performing a Timing Simulation with DVE & QuickSim II Software Performing a Timing Simulation with QuickHDL Software Performing a Timing Analysis with QuickPath Software Device Programming Programming Altera Devices Related Links: MAX+PLUS II Development Software Altera Programming Hardware Mentor Graphics web site (http://www.mentor.com) Feedback Did this information help you? If no, please log onto mySupport to file a technical request or enhancement. Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution. 给本页评分

请填写反馈意见   注册索取最新邮件通知

主页 | 产品 | 支持 | 最终市场 | 技术中心 | 教育与活动 | 公司介绍 | 在线购买  mySupport | 器件 | 软件 | IP | 设计范例 | 参考设计  联系我们 | 站点帮助 | 网站导航 | 个人信息 | 法律申明  Copyright © 1995-2008 Altera International Limited, 香港九龙观塘观塘道388号创纪之城1期1座9楼11-18室 Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus和MegaCore是Altera公司的商标。