Instantiating RAM & ROM Functions in VHDL
The MAX+PLUS® II/Synopsys interface offers full support for the memory capabilities of the FLEX® 10K device family, including synchronous and asynchronous RAM and ROM, cycle-shared dual port RAM, dual-port RAM, single-Clock FIFO, and dual-clock FIFO functions. You can use the Altera®-provided genmem utility to generate functional simulation models and timing models for these functions. Type genmem  at the UNIX prompt to display information on how to use this utility, as well as a list of the functions you can generate.
To instantiate a RAM or ROM function in VHDL, follow these steps:
- Use the genmem utility to generate a memory model by typing the following command at the UNIX prompt:
genmem <memory type> <memory size> -vhdl
For example: genmem asynrom 256x15 -vhdl
- Create a VHDL design that incorporates the text from the genmem-generated Component Declaration, <memory name>.cmp, and instantiate the <memory name> function.
Figure 1 shows a VHDL design that instantiates asyn_rom_256x15.vhd, a 256 x 15 ROM function.
| Figure 1. VHDL Design File with ROM Instantiation (tstrom.vhd)
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
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ENTITY tstrom IS
PORT (
addr : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
memenab : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR (14 DOWNTO 0));
END tstrom;
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ARCHITECTURE behavior OF tstrom IS
COMPONENT asyn_rom_256x15
-- pragma translate_off
GENERIC (LPM_FILE : string);
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-- pragma translate_on
PORT (Address : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
MemEnab : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END COMPONENT;
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BEGIN
u1: asyn_rom_256x15
-- pragma translate_off
GENERIC MAP (LPM_FILE => "u1.hex")
-- pragma translate_on
PORT MAP (Address => addr, MemEnab => memenab, Q =>q);
END behavior;
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- (Optional for RAM functions) Specify an initial memory content file:
- For ROM functions, you must specify the filename of an initial memory content file in the Intel hexadecimal format (.hex) or the Altera® Memory Initialization File (.mif) format in the Generic Map Clause, with the
LPM_FILE parameter. See Figure 1. The filename must be the same as the instance name; e.g., the u1 instance name must be unique throughout the whole project, and must contain only valid VHDL name characters. The initialization file must reside in the directory containing the project's design files.
- For RAM functions, specifying a memory initialization file is optional. If you want to use it, you must specify it in the Generic Map Clause as described above. If you do not use an initialization file, you should not declare or use the Generic Clause.
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- The MIF format is supported only for specifying initial memory content when compiling designs within MAX+PLUS II software. You cannot use a MIF to perform simulation with Synopsys tools prior to MAX+PLUS II compilation.
- If you use an Intel hexadecimal format file and wish to simulate the design with the VHDL System Simulator (VSS) after MAX+PLUS II compilation, you should use the Synopsys intelhex utility to translate the Intel hexadecimal fomat file into a VSS-compatible Synopsys memory file. Refer to the Synopsys VHDL System Simulator Software Tool manual for details about using the intelhex utility.
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- In the VHDL design file, add the compiler directive
-- pragma translate_off before the Generic Clause and Generic Map Clause, and add -- pragma translate_on after the Generic Clause and Generic Map Clause. These directives tell the VHDL Compiler software when to stop and start synthesizing. For example, in Figure 1, the --pragma translate_off directive instructs the VHDL Compiler software to skip syntax checking until the --pragma translate_on directive is read.
- Because the VHDL Compiler software does not support the data type
string for the Generic Clause, you must also enter the following command before you read the design:
hdlin_translate_off_skip_text=true
- The timing model (.lib) generated by the genmem utility contains pin-to-pin delay information that can be used by the Synopsys Design Compiler and FPGA Compiler software. You must add this timing model to the existing library so that the compiler can access the timing information. Type the following commands at the dc_shell prompt:
read -f db flex10k[<speed grade>].db
update_lib flex10k[<speed grade>] <RAM/ROM function name>.lib |
- (Optional) Enter the following command to update your flex10k[<speed grade>].db file with the RAM/ROM timing information:
write_lib flex10k[<speed grade>] -o flex10k.db
- When you generate the EDIF netlist file from the design, include the bus structure from the RAM or ROM function(s). Go to Setting Up Synopsys Configuration Files for more information.
Continue with the steps necessary to complete your VHDL design, as described in Creating VHDL Designs for Use with MAX+PLUS II Software.
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