Instantiating RAM & ROM Functions in Verilog HDL
The MAX+PLUS® II/Synopsys interface offers full support for the memory capabilities of the FLEX® 10K device family, including synchronous and asynchronous RAM and ROM, cycle-shared dual port RAM, dual-port RAM, single-Clock FIFO, and dual-clock FIFO functions. You can use the Altera®-provided genmem utility to generate functional simulation models and timing models for these functions. Type genmem  at the UNIX prompt to display information on how to use this utility, as well as a list of the functions you can generate.
To instantiate a RAM or ROM function in Verilog HDL, follow these steps:
- Use the genmem utility to generate a memory model by typing the following command at the UNIX prompt:
genmem <memory type> <memory size> -verilog
For example: genmem asynrom 256x15 -verilog
- Create a Verilog HDL design that instantiates the <memory name> function.
Figure 1 shows a Verilog HDL design that instantiates asyn_rom_256x15.v, a 256 x 15 ROM function.
| Figure 1. Verilog HDL File with ROM Instantiation (tstrom.v)
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module tstrom (addr, enab, q);
parameter LPM_FILE = "u1.hex";
input [7:0] addr;
input enab;
output [14:0] q;
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asyn_rom_256x15
// synopsys translate_off
#(LPM_FILE)
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// synopsys translate_on
u1 (.Address(addr), .Q(q), .MemEnab(enab));
endmodule
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- (Optional for RAM functions) Specify an initial memory content file:
- For ROM functions, you must specify the filename of an initial memory content file in the Intel hexadecimal format (.hex) or the Altera® Memory Initialization File (.mif) format in the Parameter Statement, with the
LPM_FILE parameter. See Figure 1. The filename must be the same as the instance name; e.g., the u1 instance name must be unique throughout the whole project. The initialization file must reside in the directory containing the project's design files.
- For RAM functions, specifying a memory initialization file is optional. If you want to use it, you must specify it in a Parameter Statement, as described above.
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- The MIF format is supported only for specifying initial memory content when compiling designs within MAX+PLUS II software. You cannot use a MIF to perform simulation with Synopsys tools prior to MAX+PLUS II compilation.
- If you use an Intel hexadecimal format file and wish to simulate the design with the VHDL System Simulator (VSS) after MAX+PLUS II compilation, you should use the Synopsys intelhex utility to translate the Intel hexadecimal fomat file into a VSS-compatible Synopsys memory file. Refer to the Synopsys VHDL System Simulator Software Tool manual for details about using the intelhex utility.
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- In the Verilog HDL design, add
// synopsys translate_off before the Parameter Statement, and add // synopsys translate_on after the Parameter Statement. These directives tell the HDL Compiler for Verilog when to stop and start synthesizing. See Figure 1.
- The timing model (.lib) generated by the genmem utility contains pin-to-pin delay information that can be used by the Synopsys Design Compiler and FPGA Compiler software. You must add this timing model to the existing library so that the compiler can access the timing information. Type the following commands at the dc_shell prompt:
read -f db flex10k[<speed grade>].db
update_lib flex10k[<speed grade>] <RAM/ROM function name>.lib |
- (Optional) Include the following command to update your flex10k[<speed grade>].db file with the RAM/ROM timing information:
write_lib flex10k[<speed grade>] -o flex10k.db
- When you generate the EDIF netlist file from the design, include the bus structure from the RAM or ROM function(s). Go to Setting Up Synopsys Configuration Files for more information.
- Continue with the steps necessary to complete your Verilog HDL design, as described in Creating Verilog HDL Designs for Use with MAX+PLUS II Software.
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