Primitive & Old-Style Macrofunction Instantiation Example for Verilog HDL
You can instantiate the MAX+PLUS® II primitives listed in Design Compiler & FPGA Compiler Technology Libraries in Verilog HDL designs. These primitives can be used to control synthesis in the MAX+PLUS II software. You can also instantiate MAX+PLUS II megafunctions and old-style macrofunctions.
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Go to the following topics for information and examples of how to instantiate functions that are not considered to be hollow bodies, including functions in the alt_mf library, RAM and ROM, and the clklock megafunction:
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Unlike other logic functions, MAX+PLUS II primitives do not need to be defined with hollow-body functions unless you wish to simulate the design with the VHDL System Simulator (VSS) software. Any references to these primitives are resolved by the Synopsys compilers. All buffer primitives except the ATRIBUF and TRIBUF primitives also have a "don't touch" attribute already assigned to them, which prevents the Synopsys compilers from optimizing them. The Synopsys compilers also automatically treat mega- and macrofunctions that do not have corresponding synthesis library models as "black boxes."
Figure 1 shows a 4-bit full adder with registered output that also instantiates an AGLOBAL or GLOBAL primitive. This figure also illustrates the use of global Clock and global Reset pins in the MAX 7000 architecture. The design uses an old-style 7483 macrofunction, which is represented as a hollow body named fa4.
| Figure 1. 4-Bit Adder Design with Registered Output (adder.v)
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module adder (a, b, clk, rst, cout, regsum);
output cout;
output[4:1] regsum;
input[4:1] a, b;
input clk, rst;
wire[4:1] sum;
reg[4:1] regsum_int;
wire grst, gclk;
wire ci;
assign ci = 0;
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// module instantiation
fa4 u0 ( .c0(ci), .a1(a[1]), .b1(b[1]), .a2(a[2]),
.b2(b[2]), .a3(a[3]), .b3(b[3]), .a4(a[4]),
.b4(b[4]), .s1(sum[1]), .s2(sum[2]),
.s3(sum[3]), .s4(sum[4]), .c4(cout));
// For FLEX devices, GLOBAL, A_IN, and A_OUT should be replaced
// with AGLOBAL, IN1, and Y, respectively
GLOBAL u1 ( .A_IN(clk), .A_OUT(gclk));
GLOBAL u2 ( .A_IN(rst), .A_OUT(grst));
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always @(posedge gclk or negedge grst)
if ( !grst )
regsum_int = 4'b0;
else regsum_int = sum;
assign regsum = regsum_int;
endmodule
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// module declaration for fa4 module
module fa4 ( c0, a1, b1, a2, b2, a3, b3, a4, b4, s1, s2, s3, s4, c4);
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output s1, s2, s3, s4, c4;
input c0, a1, b1, a2, b2, a3, b3, a4, b4;
endmodule
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// module declaration for GLOBAL primitive
// For FLEX devices, GLOBAL, A_IN, and A_OUT should be replaced
// with AGLOBAL, IN1, and Y, respectively
module GLOBAL (A_OUT, A_IN);
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input A_IN;
output A_OUT;
endmodule
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You can analyze the 4-bit adder design with the Synopsys HDL Compiler for Verilog software. The hollow-body description of the fa4 function is required. It contains port declarations and does not include any information about the design's function or operation. However, the hollow-body description can be in the design file, as shown in Figure 1, or in a separate file, as shown in Figure 2.
| Figure 2. Hollow-Body Description of a 4-Bit Full Adder (7483)
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module fa4 ( c0, a1, b1, a2, b2, a3, b3, a4, b4, s1, s2, s3, s4, c4);
output s1, s2, s3, s4, c4;
input c0, a1, b1, a2, b2, a3, b3, a4, b4;
endmodule
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If the hollow-body description is in a separate file, you must analyze it before analyzing the higher-level function with the HDL Compiler for Verilog to produce a hollow-body component. This component contains a single level of hierarchy with input and output pins, but does not contain any underlying logic.
You can save the synthesized design as an EDIF netlist file (.edf) and compile it with the MAX+PLUS II software. After the HDL Compiler for Verilog software has successfully processed the design, it generates the schematic shown in Figure 3, which you can view with the Design Analyzer software.
Figure 3. Synthesized Design Generated by the Design Compiler
However, before you compile the EDIF netlist file with the MAX+PLUS II software, you must create the adder.lmf file, shown in Figure 3, to map the fa4 function to the equivalent MAX+PLUS II function (7483). You must then specify the LMF as LMF #2 in the expanded EDIF Netlist Reader Settings dialog box (Interfaces menu) (LMF #1 is altsyn.lmf). For more information about creating LMFs, refer to "Library Mapping Files (.lmf)" and "Library Mapping File Format" in MAX+PLUS II Help.
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Figure 3. Library Mapping File Excerpt for fa4 |
BEGIN
FUNCTION 7483 (c0, a1, b1, a2, b2, a3, b3, a4, b4,)
RETURNS (s1, s2, s3, s4, c4)
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FUNCTION "fa4" ("c0", "a1", "b1", "a2", "b2", "a3",
"b3","a4", "b4")
RETURNS ("s1", "s2", "s3", "s4", "c4")
END
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When you compile the design with the MAX+PLUS II software, you can disregard the warning "EDIF cell <name> already has LMF mapping so CONTENTS construct has been ignored". To verify the global Clock and global Reset usage, as well as the number of logic cells used, see the adder.rpt Report File generated by the MAX+PLUS II Compiler.
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