Resynthesizing a Design Using the alt_vtl Library & a MAX+PLUS II SDF Output File
Altera provides the alt_vtl.db post-synthesis library for technology mapping or resynthesis. You can use this library with the MAX+PLUS® II-generated Standard Delay Format (SDF) Output File (.sdo) to retarget and resynthesize your design for another device family by performing the following steps:
To retarget and resynthsize a design, follow these steps:
- Generate an EDIF Output File (.edo) and an SDF Output File (.sdo), as described in Compiling Projects with MAX+PLUS II Software.
- Modify your .synopsys_dc.setup file to include the following lines:
search_path = {./usr/maxplus2/synopsys/library/alt_post/syn/lib
<target library path>}; 
target_library = {<target library path>};
symbol_library = {<target library symbol file>};
link_library = {alt_vtl.db};
- In the Design Compiler or FPGA Compiler software,
type the following commands to read in the EDIF and SDF
output files:
read -f edif <design name>.edo
read_timing -load_delay net <design name>.sdo
- Type the following commands to compile
your design, report the timing information, and create an EDIF netlist file (.edf) that can be processed with the MAX+PLUS II Compiler.
compile
report_timing
write -f edif -hierarchy -o <design name>.edf
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Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
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