Converting Synopsys Timing Constraints into MAX+PLUS II-Compatible Format with the syn2acf Utility
Altera provides the syn2acf
utility, which is an interface program that converts Synopsys
timing constraints from non-hierarchical designs into the MAX+PLUS® II Assignment & Configuration
File (.acf)
format. For information on converting timing constraints from hierarchical designs, refer to Converting Synopsys Hierarchical Timing Constraints into MAX+PLUS II-Compatible Format with the gen_iacf and gen_hacf Utilities.
The syn2acf
utility requires the following input files:
- Flattened EDIF netlist file
- dc_shell script file
- Standard Delay Format (SDF) constraints
construct
- SDF timing delay construct
To use the syn2acf
utility, follow these steps:
Set the timing constraints by using one of the following methods:
 |
Start the Synopsys Design Analyzer
and specify timing constraints by choosing appropriate menu commands. |
or:
|
Create the <design
name>.cmd
file for use with a dc_shell script.
See Figure 1. |
 |
The syn2acf
utility does not support set_arrival
timing constraints for internal nodes. |
Figure 1. Sample Command File (.cmd) for Setting Timing Constraints
create_clock -period 50 -waveform {0 25} CLK
set_clock_skew -delay 2 CLK
set_input_delay 10 IN2
set_input_delay 5 -clock CLK IN1
set_output_delay 20 OUT2
set_output_delay 5 -clock CLK OUT1
set_max_delay 25 -to OUT1
set_max_delay 35 -to OUT2
set_multicycle_path 2 -to n20_reg
|
- Compile
the design and run the syn2acf
utility either from the command line or with a Design Compiler
dc
script:
|
Compile the design, then type the
following command from the UNIX prompt to start the syn2acf
utility:
/usr/maxplus2/synopsys/bin/syn2acf
<design name>  |
or:
|
Run a dc
script inside
the dc_shell
script that reads the VHDL design, compiles it, and runs the syn2acf
utility. Figure 2 shows a sample dc
script. |
|
The syn2acf
utility uses the ALT_HOME
environment variable, if it has been specified, to determine the
MAX+PLUS II system directory; otherwise, it uses the
/usr/maxplus2
directory. To specify a different MAX+PLUS II system directory
with the ALT_HOME
environment variable, you can either edit the .cshrc file to specify the correct directory or type the following command at the UNIX prompt:
setenv
ALT_HOME <MAX+PLUS II
system directory> |
Figure 2. Sample Script for Running the syn2acf Utility
/* dc_script example to interface with syn2acf */ |
|
dc_shell <<! |
|
read -f vhdl <design name>.vhd |
include <design name>.cmd |
/*set timing constraints*/ |
compile
|
current_design=<design name> |
|
include /usr/maxplus2/synopsys/bin/syn2acf.cmd |
/*generate required files*/ |
sh /usr/maxplus2/synopsys/bin/syn2acf <design name> |
/*invoke syn2acf utility*/ |
quit |
|
! |
|
|
The
syn2acf
utility cannot support maximum Clock frequency (fMAX)
correctly if more than one Clock skew is specified in the dc_shell
command script. This problem occurs because the Synopsys write_script
command drops the Clock skew information for the registers. The
syn2acf
utility will use the last Clock skew number to calculate fMAX. |
The sample dc
script includes the Altera®-provided syn2acf.cmd
file, shown in Figure 3, to generate the required input
files for the syn2acf
utility.
Figure 3. Altera-Provided syn2acf.cmd File
ungroup -flatten -all
write -f edif
write_script > altsyn.dc
write_constraints -format sdf -cover_design
write_timing -format sdf
|
All timing assignments generated by
the syn2acf
utility are written to the Timing Requirement Assignments Section
of the project's ACF, with the assignment source identifier
{synopsys}
at the end of each line. Figure 4
shows a sample ACF excerpt that contains Synopsys timing constraints
generated by the syn2acf
utility.
Figure 4. Sample ACF Excerpt with Synopsys Timing Constraints
TIMING_POINT
BEGIN
"|OUT2" : TCO = 15.00ns {synopsys};
"|IN1" : TPD = 10.00ns {synopsys};
"|IN2" : TPD = 5.00ns {synopsys};
"|OUT1" : TCO = 20.00ns {synopsys};
"|IN1" : TSU = 20.00ns {synopsys};
"|IN2" : TSU = 117.00ns {synopsys};
"|CLK" : FREQUENCY = 50.00ns {synopsys};
"|n10_reg" : FREQUENCY = 100.00ns {synopsys};
END;
|
Altera provides sample files for these utilities in the /usr/maxplus2/synopsys/bin directory.
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