Creating VHDL Designs for Use with MAX+PLUS II Software
You can create VHDL design files with the
MAX+PLUS® II Text Editor or another standard text editor and save them in the appropriate directory for your project. The MAX+PLUS II Text Editor offers the following advantages:
- VHDL templates are available with the VHDL Templates command (Templates menu). These templates are also available in the ASCII vhdl.tmp file, which is located in the /usr/maxplus2 directory.
- If you use the MAX+PLUS II Text Editor to create your VHDL design, you can use the Syntax Coloring command (Options menu). The Syntax Coloring feature displays keywords and other elements of text in text files in different colors to distinguish them from other forms of syntax.
Once you have created a VHDL design, you can use the Design Compiler or FPGA Compiler to synthesize and optimize it, and then generate an EDIF netlist file that can be processed with the MAX+PLUS II software.
To create a VHDL design that can be synthesized and optimized with the Design Compiler or FPGA Compiler, follow these steps:
- Instantiate logic functions with a Component Instantiation, and include a Component Declaration for each function. Altera provides simulation models for the following types of logic functions:
You can also instantiate any other Altera macrofunction or non-parameterized megafunction, i.e., functions not listed above, for which no simulation models or technology library support is available. These functions are treated as "black boxes" during processing with the Design Compiler or FPGA Compiler. See Primitive & Old-Style Macrofunction Instantiation Example for VHDL for an example.
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For information on MAX+PLUS II primitives, megafunctions, and macrofunctions, choose Primitives, Megafunctions/LPM, or Old-Style Macrofunctions from the MAX+PLUS II Help menu. When searching for information on the alt_mf library functions, drop the initial "a_" from the function name.
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- (Optional) If you instantiate a "black box" logic function for which no simulation/techology library support is available, create a hollow-body design description in order to prevent the Design Compiler or FPGA Compiler from issuing a warning message. See Primitive & Old-Style Macrofunction Instantiation Example for VHDL for an example.
- Once you have created a VHDL design, you can analyze it, synthesize it, (optional) perform a functional simulation, and generate an EDIF netlist file that can be imported into the MAX+PLUS II software. Go to the following topics for instructions:
Installing the Altera-provided MAX+PLUS II/Synopsys Logic interface on your computer automatically creates the following VHDL sample files:
- /usr/maxplus2/examples/mentor/examples/ministate.vhd
- /usr/maxplus2/examples/mentor/examples/count8.vhd
- /usr/maxplus2/examples/mentor/examples/tstrom.vhd
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Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
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