Assigning a Device & Clock Frequency (fMAX)
You can specify the desired Clock frequency (called fMAX in the MAX+PLUS® II software) and the target device family before synthesizing and optimizing the design with the FPGA Express software. You can optionally select a specific device and speed grade within the target device family. These assignments are stored in the design's Assignment & Configuration File, <design name>.acf, which is generated automatically by the FPGA Express software.
To assign a device or device family and the Clock frequency, follow these steps:
- If you have not already done so, identify the top-level design for your project from the Design Sources window. Select the top-level design from the Top-Level Design drop-down list on the toolbar. The Create Implementation dialog box is displayed.
- Enter an implementation name in the Implementation Name box. If you do not enter a name, FPGA Express software automatically creates a unique implementation name.
- Select Altera from the Vendor list.
- Select the appropriate Altera device family from the Family list.
- (Optional) Select a specific device from the Device list, and select a specific speed grade from the Speed Grade list.
- Type the desired Clock frequency in the Clock Frequency text box. This Clock frequency is used as the default value for all Clock signals in the design.
- (Optional) Select speed/area and CPU effort settings, as described in Specifying the Speed/Area & CPU Effort Settings with the FPGA Express Software.
- Continue with the steps necessary to process your design, as described in Synthesizing & Optimizing VHDL or Verilog HDL Files with FPGA Express Software.
Related Topics:
- Go to the following sources for related information:
- FPGA Express Help
- "Guidelines for Achieving Maximum Speed Performance" in MAX+PLUS II Help
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Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
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