Instantiating RAM & ROM Functions in VHDL
The MAX+PLUS® II/Synopsys interface offers full support for the memory capabilities of the FLEX®10K device family, including synchronous and asynchronous RAM and ROM, cycle-shared dual port RAM, dual-port RAM, single-Clock FIFO, and dual-clock FIFO functions. Altera recommends using the LPM functions lpm_ram_dq, lpm_ram_io, and lpm_rom to instantiate synchronous and asynchronous RAM and ROM. However, if you wish to enter cycle-shared dual port RAM (csdpram), dual-port RAM (altdpram), single-Clock FIFO (scfifo), and dual-clock FIFO (dcfifo) functions, or if you wish to create simulation models for any supported RAM or ROM function, you can use the Altera-provided genmem utility. Instantiations created with genmem for use with other Synopsys products, such as FPGA Compiler or Design Compiler, are supported for backward compatibility. Type genmem  at the DOS or UNIX prompt to display information on how to use this utility, as well as a list of the functions you can generate.
To instantiate an lpm_ram_dq, lpm_ram_io, or lpm_rom function:
To instantiate other RAM and ROM functions in VHDL, follow these steps:
- Use the genmem utility to generate a memory model by typing the following command at the DOS or UNIX prompt:
genmem <memory type> <memory size> -vhdl
For example: genmem scfifo 16x8 -vhdl
Create a VHDL design that incorporates the text from the genmem-generated Component Declaration, <memory name>.cmp, and instantiate the <memory name>.vhd function. The genmem utility produces files with descriptive names that typically include both the memory type and the memory size (e.g., scfifo_16x8_d.vhd).
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In MAX+PLUS II version 8.3 and lower, running genmem on a PC always creates files named as genmem.vhd, genmem.cmp, and genmem.v, regardless of the memory type and memory size you specify. |
(Optional for RAM functions) Specify an initial memory content file:
- For ROM functions, you must specify the filename of an initial memory content file in the Intel hexadecimal format (.hex) or the Altera® Memory Initialization File (.mif) format in the Generic Map Clause, with the
LPM_FILE parameter. The filename must be the same as the instance name; e.g., the u1 instance name shown in Figure 1 must be unique throughout the whole project, and must contain only valid VHDL name characters. The initialization file must reside in the directory containing the project's design files.
- For RAM functions, specifying memory initialization file is optional. If you want to use it, you must specify it in the Generic Map Clause as described above. If you do not use an initialization file, you should not declare or use the Generic Clause.
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- The MIF format is supported only for specifying initial memory content when compiling designs within MAX+PLUS II software. You cannot use an MIF to perform simulation with Synopsys tools prior to MAX+PLUS II compilation.
- If you use an Intel hexadecimal format file and wish to simulate the file with the VHDL System Simulator (VSS) after MAX+PLUS II compilation, you should use the Synopsys intelhex utility to translate the Intel hexadecimal fomat file into a VSS-compatible Synopsys memory file. Refer to the Synopsys VHDL System Simulator Software Tool manual for details about using the intelhex utility.
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- Continue with the steps necessary to complete your VHDL design, as described in Creating VHDL Designs for Use with MAX+PLUS II Software.
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