Entering Resource, Device & Global Logic Synthesis Assignments
The MAX+PLUS® II software allows you to enter a variety of resource, device, and global logic synthesis assignments for your projects.
Resource assignments are used to assign logic functions to a particular
pin, logic cell, I/O cell, embedded cell, row, column, Logic Array
Block (LAB), Embedded Array Block (EAB), chip, clique, local routing,
logic option, timing requirement, or connected pin group. With MAX+PLUS II software, you can enter all types of resource, device, and global logic synthesis assignments
with Assign menu commands. You can also enter pin, logic cell,
I/O cell, embedded cell, LAB, EAB, row, and column assignments
in the MAX+PLUS II Floorplan Editor. The Assign menu commands
and the Floorplan Editor all save assignment information in the
ASCII Assignment & Configuration File (.acf)
for the project.
In the Synopsys FPGA Express software,
you can assign a limited subset of these assignments in the Create Implementation dialog box, in the Options dialog box, and
by specifying options in constraint tables. These attributes are incorporated into the ACF generated by the FPGA Express software. Refer to the following topics for more information:
Related Links:
- Go to the following sources for related information:
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Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
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