Performing a Pre-Routing or Functional Simulation with VSS Software
After you have synthesized and optimized a VHDL or Verilog HDL design with the Design Compiler or FPGA Compiler software, you can perform a pre-routing or functional simulation with the Synopsys VHDL System Simulator (VSS) software.
To perform a pre-routing/functional simulation, follow these steps:
- Be sure to set up the working environment correctly, as described in the following topics:
- Create a VHDL or Verilog HDL design file that follows the guidelines described in one of the following topics:
- Synthesize and optimize your design with the Design Compiler or FPGA Compiler, as described in Synthesizing & Optimizing VHDL & Verilog HDL Files with Design Compiler or FPGA Compiler Software.
- Save your design as a VHDL Design File (.vhd).
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VSS requires each architecture/entity pair in a VHDL Design File to have a configuration. The Configuration Declaration is necessary for simulation, but not for synthesis. |
- Use VSS and one of the Altera pre-routing functional simulation libraries to simulate the design.
- When you are ready to compile your project with MAX+PLUS II software, save the design as an EDIF netlist file (.edf), then process it as described in Compiling Projects with MAX+PLUS II Software.
Related Links:
- Refer to the following sources for related information:
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