Project Simulation Flow
Figure 1 shows the project simulation flow for the MAX+PLUS® II/Synopsys interface.
Figure 1. MAX+PLUS II/Synopsys Project Simulation Flow
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Altera-provided items are shown in blue. |
The MAX+PLUS II/Synopsys design environment fully supports design verification with the Synopsys VHDL System Simulator (VSS). For pre-route simulation, you can simulate a design that has been compiled with one of the Synopsys compilers. For post-route simulation, you can simulate the VHDL Output File (.vho) that MAX+PLUS II® software generates during project compilation.
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